9,407 research outputs found
Recommended from our members
Design of a 3 GHz fine resolution LC DCO
In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning. Both delta-sigma modulator and capacitive divider circuit are implemented to achieve a finer resolution and a larger dynamic range. The LC-oscillator has a coarse tuning range from 3.05 GHz to 3.85 GHz and a fine tuning range of 50MHz. It features a phase noise level of -115dBc/Hz at 1MHz frequency offset and consumes 5.4mW. Efficient simulation methodology is explored. Finally, this DCO is simulated in an All-Digital Phase Locked Loop (ADPLL) with other ideal behavior blocks implemented using Verilog-A, and the performance of the DCO is evaluated.Electrical and Computer Engineerin
Recommended from our members
Noise shaping Asynchronous SAR ADC based time to digital converter
Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin
Recommended from our members
High Performance Local Oscillator Design for Next Generation Wireless Communication
Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances.
The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication.
The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges.
To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen-
eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation.
To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept.
In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes.
Finally, Chapter 6 presents the conclusion of this thesis
On the design of software and hardware for a WSN transmitter
Software defined radios (SDR) are booming. However, for a final breakthrough these systems need to be versatile, inexpensive and easy to program. In this paper a next step is taken to meet all these requirements. Our hardware consists of a computer with an affordable data acquisition (DAQ) card and a cheap self-made single-stage up-converter. The software is written in the slow learning-curve graphical programming environment LabVIEW. To prove the versatility of our SDR transmitter concept, we send packets with the wireless sensor networks (WSN) protocol IEEE 802.15.4, which are received by an existing packet sniffer
A Wide Range and High Swing Charge Pump for Phase Locked Loop in Phasor Measurement Unit
ยฉ 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Phasor Measurement Units are widely utilized in power systems to provide synchrophasor data for a verity of applications, mainly performed by Energy Management Systems (EMS). Synchrophasors are measured at different parts of the network and transmitted to Phasor Data Concentrator (PDC) at a rate of 30-60 samples per second. The synchronization is done by means of a phase locked oscillator inside PMU which uses clock signal of the Global Positioning System (GPS). In this paper a novel charge pump with an appropriate operation capability in phaselocked-loops is presented. By using this phase locked loop in phasor measurement unit, the total performance of this circuit will be improved. The proposed charge pump uses current mirror techniques in order to achieve a wide range of output voltage to control the oscillator and also has a good performance in a wide frequency range from 33MHz to 555MHz. This circuit is designed and simulated in TSMC 0.18ฮผm CMOS technology. The proposed charge pump only consumes 390ฮผW power in supply voltage of 1.8V at 500MHz and has a maximum current of 16.43ฮผA with an acceptable current matching between source and sink currents. It is also capable to be used in a wide frequency range and low power applications
Switched Capacitor Loop Filter ์ Source Switched Charge Pump ๋ฅผ ์ด์ฉํ Phase-Locked Loop ์ ์ค๊ณ
ํ์๋
ผ๋ฌธ(์์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022.2. ์ ๋๊ท .This thesis proposes a low integrated RMS jitter and low reference spur phase locked loop (PLL) using a switched capacitor loop filter and source switched charge pump. The PLL employs a single tunable charge pump which reduces current mis match across wide control voltage range and charge sharing effect to get high perfor mance of reference spur level. The switched capacitor loop filter is adopted to achieve insensitivity to temperature, supply voltage, and process variation of a resistor. The proposed PLL covers a wide frequency range and has a low integrated RMS jitter and low reference spur level to target various interface standards. The mechanism of switched capacitor loop filter and source switched charge pump is analyzed. Fabricated in 40 nm CMOS technology, the proposed analog PLL provides four phase for a quarter-rate transmitter, consumes 6.35 mW at 12 GHz using 750 MHz reference clock, and occupies an 0.008 mm2 with an integrated RMS jitter (10 kHz to 100 MHz) of 244.8 fs. As a result, the PLL achieves a figure of merit (FoM) of -244.2 dB with high power efficiency of 0.53 mW/GHz, and reference spur level is -60.3 dBc.๋ณธ ๋
ผ๋ฌธ์์๋ ๋ฎ์ RMS jitter ์ ๋ฎ์ ๋ ํผ๋ฐ์ค ์คํผ๋ฅผ ๊ฐ์ง๋ฉฐ ์ค์์น์ถ์ ๊ธฐ ๋ฃจํ ํํฐ์ ์์ค ์ค์์น ์ ํ ํํ๋ฅผ ์ด์ฉํ PLL ์ ์ ์ํ๋ค. ์ ์๋ PLL ์ ๋ ํผ๋ฐ์ค ์คํผ์ ์ฑ๋ฅ์ ์ํด ๋์ ์ปจํธ๋กค ์ ์์ ๋ฒ์ ๋์ ์ ๋ฅ์ ์ค์ฐจ๋ฅผ ์ค์ฌ์ฃผ๊ณ ์ ํ ๊ณต์ ํจ๊ณผ๋ฅผ ์ค์ฌ์ฃผ๋ ํ๋์ ์กฐ์ ๊ฐ๋ฅํ ์ ํ ํํ๋ฅผ ์ฌ์ฉํ์๋ค. ์ ํญ์ ์จ๋, ๊ณต๊ธ ์ ์, ๊ณต์ ๋ณํ์ ๋ฐ๋ฅธ ๋ฏผ๊ฐ๋๋ฅผ ๋ฎ์ถ๊ธฐ ์ํด ์ค์์น ์ถ์ ๊ธฐ ๋ฃจํ ํํฐ๊ฐ ์ฌ์ฉ๋์๋ค. ๋ค์ํ ์ธํฐํ์ด์ค ํ์ค์ ์ง์ํ๊ธฐ ์ํด ์ ์ํ๋ PLL ์ ๋์ ์ฃผํ์ ๋ฒ์๋ฅผ ์ง์ํ๊ณ ๋ฎ์ RMS jitter ์ ๋ฎ์ ๋ ํผ๋ฐ์ค ์คํผ๋ฅผ ๊ฐ๋๋ค. ์ค์์น ์ถ์ ๊ธฐ ๋ฃจํ ํํฐ์ ์์ค ์ค์์น ์ ํ ํํ์ ๋์ ์๋ฆฌ์ ๋ํด ๋ถ์ํ์๋ค. 40 nm CMOS ๊ณต์ ์ผ๋ก ์ ์๋์์ผ๋ฉฐ, ์ ์๋ ํ๋ก๋ quarter-rate ์ก์ ๊ธฐ๋ฅผ ์ํด 4 ๊ฐ์ phase ๋ฅผ ๋ง๋ค์ด๋ด๋ฉฐ 750 MHz ์ ๋ ํผ๋ฐ์ค ํด๋ฝ์ ์ด์ฉํ์ฌ 12 GHz ์์ 6.35 mW ์ power ๋ฅผ ์๋ชจํ๊ณ 0.008mm2 ์ ์ ํจ ๋ฉด์ ์ ์ฐจ์งํ๊ณ 10 kHz ๋ถํฐ 100 MHz ๊น์ง ์ ๋ถํ์ ๋์ RMS jitter ๊ฐ์ 244.8fs ์ด๋ค. ์ ์ํ๋ PLL ์ -244.2 dB ์ FoM, 0.53 mW/GHz ์ power ํจ์จ์ ๋ฌ์ฑํ์ผ๋ฉฐ ๋ ํผ๋ฐ์ค ์คํผ๋ -60.3 dBc ์ด๋คCHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 3
CHAPTER 2 BACKGROUNDS 4
2.1 CLOCK GENERATION IN SERIAL LINK 4
2.2 PLL BUILDING BLOCKS 6
2.2.1 OVERVIEW 6
2.2.2 PHASE FREQUENCY DETECTOR 7
2.2.3 CHARGE PUMP AND LOOP FILTER 9
2.2.4 VOLTAGE CONTROLLED OSCILLATOR 10
2.2.5 FREQUENCY DIVIDER 13
2.3 PLL LOOP ANALYSIS 15
CHAPTER 3 PLL WITH SWITCHED CAPACITOR LOOP FILTER AND SOURCE SWITCHED CHARGE PUMP 19
3.1 DESIGN CONSIDERATION 19
3.2 PROPOSED ARCHITECTURE 21
3.3 CIRCUIT IMPLEMENTATION 23
3.3.1 PHASE FREQUENCY DETECTOR 23
3.3.2 SOURCE SWITCHED CHARGE PUMP 26
3.3.3 SWITCHED CAPACITOR LOOP FILTER 30
3.3.4 VOLTAGE CONTROLLED OSCILLATOR 35
3.3.5 POST VCO AMPLIFIER 39
3.3.6 FREQUENCY DIVIDER 40
CHAPTER 4 MEASUREMENT RESULTS 43
4.1 CHIP PHOTOMICROGRAPH 43
4.2 MEASUREMENT SETUP 45
4.3 MEASURED PHASE NOISE AND REFERENCE SPUR 47
4.4 PERFORMANCE SUMMARY 50
CHAPTER 5 CONCLUSION 52
BIBLIOGRAPHY 53
์ด ๋ก 58์
An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems
The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works
- โฆ