19,026 research outputs found
XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference
Binary Neural Networks (BNNs) are promising to deliver accuracy comparable to
conventional deep neural networks at a fraction of the cost in terms of memory
and energy. In this paper, we introduce the XNOR Neural Engine (XNE), a fully
digital configurable hardware accelerator IP for BNNs, integrated within a
microcontroller unit (MCU) equipped with an autonomous I/O subsystem and hybrid
SRAM / standard cell memory. The XNE is able to fully compute convolutional and
dense layers in autonomy or in cooperation with the core in the MCU to realize
more complex behaviors. We show post-synthesis results in 65nm and 22nm
technology for the XNE IP and post-layout results in 22nm for the full MCU
indicating that this system can drop the energy cost per binary operation to
21.6fJ per operation at 0.4V, and at the same time is flexible and performant
enough to execute state-of-the-art BNN topologies such as ResNet-34 in less
than 2.2mJ per frame at 8.9 fps.Comment: 11 pages, 8 figures, 2 tables, 3 listings. Accepted for presentation
at CODES'18 and for publication in IEEE Transactions on Computer-Aided Design
of Circuits and Systems (TCAD) as part of the ESWEEK-TCAD special issu
HardScope: Thwarting DOP with Hardware-assisted Run-time Scope Enforcement
Widespread use of memory unsafe programming languages (e.g., C and C++)
leaves many systems vulnerable to memory corruption attacks. A variety of
defenses have been proposed to mitigate attacks that exploit memory errors to
hijack the control flow of the code at run-time, e.g., (fine-grained)
randomization or Control Flow Integrity. However, recent work on data-oriented
programming (DOP) demonstrated highly expressive (Turing-complete) attacks,
even in the presence of these state-of-the-art defenses. Although multiple
real-world DOP attacks have been demonstrated, no efficient defenses are yet
available. We propose run-time scope enforcement (RSE), a novel approach
designed to efficiently mitigate all currently known DOP attacks by enforcing
compile-time memory safety constraints (e.g., variable visibility rules) at
run-time. We present HardScope, a proof-of-concept implementation of
hardware-assisted RSE for the new RISC-V open instruction set architecture. We
discuss our systematic empirical evaluation of HardScope which demonstrates
that it can mitigate all currently known DOP attacks, and has a real-world
performance overhead of 3.2% in embedded benchmarks
Emergent behaviour in a chlorophenol-mineralising three-tiered microbial `food web'
Anaerobic digestion enables the water industry to treat wastewater as a
resource for generating energy and recovering valuable by-products. The
complexity of the anaerobic digestion process has motivated the development of
complex models. However, this complexity makes it intractable to pin-point
stability and emergent behaviour. Here, the widely used Anaerobic Digestion
Model No. 1 (ADM1) has been reduced to its very backbone, a syntrophic
two-tiered microbial food chain and a slightly more complex three-tiered
microbial food web, with their stability analysed as function of the inflowing
substrate concentration and dilution rate. Parameterised for phenol and
chlorophenol degradation, steady-states were always stable and non-oscillatory.
Low input concentrations of chlorophenol were sufficient to maintain
chlorophenol- and phenol-degrading populations but resulted in poor conversion
and a hydrogen flux that was too low to sustain hydrogenotrophic methanogens.
The addition of hydrogen and phenol boosted the populations of all three
organisms, resulting in the counterintuitive phenomena that (i) the phenol
degraders were stimulated by adding hydrogen, even though hydrogen inhibits
phenol degradation, and (ii) the dechlorinators indirectly benefitted from
measures that stimulated their hydrogenotrophic competitors; both phenomena
hint at emergent behaviour.Comment: 19 pages, 8 figure
Leveraging RISC-V to build an open-source (hardware) OS framework for reconfigurable IoT devices
With the growing interest in RISC-V systems and the endless possi bilities of creating customized hardware architectures, we introduce
the first proof of concept (PoC) implementation of ChamelIoT, the
first open-source agnostic hardware operating system (OS) frame work for reconfigurable Internet of Things (IoT) low-end devices. At
this stage, ChamelIoT, leveraging the Rocket Custom Co-Processor
Interface (RoCC), provides hardware acceleration support for thread
management and scheduling of three different OSes: RIOT, Zephyr,
and FreeRTOS. This paper overviews the overall ChamelIoT archi tecture and describes the implementation details of the current PoC
deployment. Our first experiments were carried out on a Xilinx
Arty-35T FPGA Evaluation kit and the preliminary results are very
promising, showing that the desired agnosticism and flexibility can
be achieved with determinism and performance advantages at a
reasonable cost of hardware resources
BRISC-V emulator: a standalone, installation-free, browser-based teaching tool
Many computer organization and computer architecture classes have recently started adopting the RISC-V architecture as an alternative to proprietary RISC ISAs and architectures. Emulators are a common teaching tool used to introduce students to writing assembly. We present the BRISC-V (Boston University RISC-V) Emulator and teaching tool, a RISC-V emulator inspired by existing RISC and CISC emulators. The emulator is a web-based, pure javascript implementation meant to simplify deployment, as it does not require maintaining support for different operating systems or any installation. Here we present the workings, usage, and extensibility of the BRISC-V emulator.Published versio
The future of Cybersecurity in Italy: Strategic focus area
This volume has been created as a continuation of the previous one, with the aim of outlining a set of focus areas and actions that the Italian Nation research community considers essential. The book touches many aspects of cyber security, ranging from the definition of the infrastructure and controls needed to organize cyberdefence to the actions and technologies to be developed to be better protected, from the identification of the main technologies to be defended to the proposal of a set of horizontal actions for training, awareness raising, and risk management
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA
Memory consistency models (MCMs) which govern inter-module interactions in a
shared memory system, are a significant, yet often under-appreciated, aspect of
system design. MCMs are defined at the various layers of the hardware-software
stack, requiring thoroughly verified specifications, compilers, and
implementations at the interfaces between layers. Current verification
techniques evaluate segments of the system stack in isolation, such as proving
compiler mappings from a high-level language (HLL) to an ISA or proving
validity of a microarchitectural implementation of an ISA.
This paper makes a case for full-stack MCM verification and provides a
toolflow, TriCheck, capable of verifying that the HLL, compiler, ISA, and
implementation collectively uphold MCM requirements. The work showcases
TriCheck's ability to evaluate a proposed ISA MCM in order to ensure that each
layer and each mapping is correct and complete. Specifically, we apply TriCheck
to the open source RISC-V ISA, seeking to verify accurate, efficient, and legal
compilations from C11. We uncover under-specifications and potential
inefficiencies in the current RISC-V ISA documentation and identify possible
solutions for each. As an example, we find that a RISC-V-compliant
microarchitecture allows 144 outcomes forbidden by C11 to be observed out of
1,701 litmus tests examined. Overall, this paper demonstrates the necessity of
full-stack verification for detecting MCM-related bugs in the hardware-software
stack.Comment: Proceedings of the Twenty-Second International Conference on
Architectural Support for Programming Languages and Operating System
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