A new VLSI architecture for a single-chip-type Reed-Solomon decoder

A new very large scale integration (VLSI) architecture for implementing Reed-Solomon (RS) decoders that can correct both errors and erasures is described. This new architecture implements a Reed-Solomon decoder by using replication of a single VLSI chip. It is anticipated that this single chip type RS decoder approach will save substantial development and production costs. It is estimated that reduction in cost by a factor of four is possible with this new architecture. Furthermore, this Reed-Solomon decoder is programmable between 8 bit and 10 bit symbol sizes. Therefore, both an 8 bit Consultative Committee for Space Data Systems (CCSDS) RS decoder and a 10 bit decoder are obtained at the same time, and when concatenated with a (15,1/6) Viterbi decoder, provide an additional 2.1-dB coding gain

VLSI architecture for a Reed-Solomon decoder

A basic single-chip building block for a Reed-Solomon (RS) decoder system is partitioned into a plurality of sections, the first of which consists of a plurality of syndrome subcells each of which contains identical standard-basis finite-field multipliers that are programmable between 10 and 8 bit operation. A desired number of basic building blocks may be assembled to provide a RS decoder of any syndrome subcell size that is programmable between 10 and 8 bit operation

Recent advances in coding theory for near error-free communications

Channel and source coding theories are discussed. The following subject areas are covered: large constraint length convolutional codes (the Galileo code); decoder design (the big Viterbi decoder); Voyager's and Galileo's data compression scheme; current research in data compression for images; neural networks for soft decoding; neural networks for source decoding; finite-state codes; and fractals for data compression

A comparison of VLSI architectures for time and transform domain decoding of Reed-Solomon codes

It is well known that the Euclidean algorithm or its equivalent, continued fractions, can be used to find the error locator polynomial needed to decode a Reed-Solomon (RS) code. It is shown that this algorithm can be used for both time and transform domain decoding by replacing its initial conditions with the Forney syndromes and the erasure locator polynomial. By this means both the errata locator polynomial and the errate evaluator polynomial can be obtained with the Euclidean algorithm. With these ideas, both time and transform domain Reed-Solomon decoders for correcting errors and erasures are simplified and compared. As a consequence, the architectures of Reed-Solomon decoders for correcting both errors and erasures can be made more modular, regular, simple, and naturally suitable for VLSI implementation

Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code

[EN] In this work, we present a new architecture for soft-decision Reed-Solomon (RS) Low-Complexity Chase (LCC) decoding. The proposed architecture is scalable and can be used for a high number of test vectors. We propose a novel Multiplicity Assignment stage that sorts and stores only the location of the errors inside the symbols and the powers of a that identify the positions of the symbols in the frame. Novel schematics for the Syndrome Update and Symbol Modification blocks that are adapted to the proposed sorting stage are also presented. We also propose novel solutions for the problems that arise when a high number of test vectors is processed. We implemented three decoders: a h = 4 LCC decoder and two decoders that only decode 31 and 60 test vectors of true h = 5 and h = 6 LCC decoders, respectively. For example, our h = 4 decoder requires 29% less look-up tables in Virtex-V Field Programmable Gate Array (FPGA) devices than the best soft-decision RS decoder published to date, while has a 0.07 dB coding gain over that decoder.This research was funded by the Spanish Ministerio de Economia y Competitividad and FEDER grant number TEC2015-70858-C2-2-RTorres Carot, V.; Valls Coquillat, J.; Canet Subiela, MJ.; García Herrero, FM. (2019). Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code. Electronics. 8(1):1-13. https://doi.org/10.3390/electronics8010010S11381Cideciyan, R., Gustlin, M., Li, M., Wang, J., & Wang, Z. (2013). Next generation backplane and copper cable challenges. IEEE Communications Magazine, 51(12), 130-136. doi:10.1109/mcom.2013.6685768Koetter, R., & Vardy, A. (2003). Algebraic soft-decision decoding of reed-solomon codes. IEEE Transactions on Information Theory, 49(11), 2809-2825. doi:10.1109/tit.2003.819332Sudan, M. (1997). Decoding of Reed Solomon Codes beyond the Error-Correction Bound. Journal of Complexity, 13(1), 180-193. doi:10.1006/jcom.1997.0439Guruswami, V., & Sudan, M. (1999). Improved decoding of Reed-Solomon and algebraic-geometry codes. IEEE Transactions on Information Theory, 45(6), 1757-1767. doi:10.1109/18.782097Jiang, J., & Narayanan, K. R. (2008). Algebraic Soft-Decision Decoding of Reed–Solomon Codes Using Bit-Level Soft Information. IEEE Transactions on Information Theory, 54(9), 3907-3928. doi:10.1109/tit.2008.928238Jiangli Zhu, Xinmiao Zhang, & Zhongfeng Wang. (2009). Backward Interpolation Architecture for Algebraic Soft-Decision Reed–Solomon Decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(11), 1602-1615. doi:10.1109/tvlsi.2008.2005575Jiangli Zhu, & Xinmiao Zhang. (2008). Efficient VLSI Architecture for Soft-Decision Decoding of Reed–Solomon Codes. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(10), 3050-3062. doi:10.1109/tcsi.2008.923169Zhongfeng Wang, & Jun Ma. (2006). High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed–Solomon Codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(9), 937-950. doi:10.1109/tvlsi.2006.884046Zhang, X. (2006). Reduced Complexity Interpolation Architecture for Soft-Decision Reed–Solomon Decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14(10), 1156-1161. doi:10.1109/tvlsi.2006.884177Xinmiao Zhang, & Parhi, K. K. (2005). Fast factorization architecture in soft-decision Reed-Solomon decoding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13(4), 413-426. doi:10.1109/tvlsi.2004.842914Bellorado, J., & Kavcic, A. (2010). Low-Complexity Soft-Decoding Algorithms for Reed–Solomon Codes—Part I: An Algebraic Soft-In Hard-Out Chase Decoder. IEEE Transactions on Information Theory, 56(3), 945-959. doi:10.1109/tit.2009.2039073García-Herrero, F., Valls, J., & Meher, P. K. (2011). High-Speed RS(255, 239) Decoder Based on LCC Decoding. Circuits, Systems, and Signal Processing, 30(6), 1643-1669. doi:10.1007/s00034-011-9327-4Zhang, W., Wang, H., & Pan, B. (2013). Reduced-Complexity LCC Reed–Solomon Decoder Based on Unified Syndrome Computation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(5), 974-978. doi:10.1109/tvlsi.2012.2197030Peng, X., Zhang, W., Ji, W., Liang, Z., & Liu, Y. (2015). Reduced-Complexity Multiplicity Assignment Algorithm and Architecture for Low-Complexity Chase Decoder of Reed-Solomon Codes. IEEE Communications Letters, 19(11), 1865-1868. doi:10.1109/lcomm.2015.2477495Lin, Y.-M., Hsu, C.-H., Chang, H.-C., & Lee, C.-Y. (2014). A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(7), 2110-2118. doi:10.1109/tcsi.2014.2298282Wu, Y. (2015). New Scalable Decoder Architectures for Reed–Solomon Codes. IEEE Transactions on Communications, 63(8), 2741-2761. doi:10.1109/tcomm.2015.2445759Garcia-Herrero, F., Canet, M. J., Valls, J., & Meher, P. K. (2012). High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(3), 568-573. doi:10.1109/tvlsi.2010.210396

Architectures for soft-decision decoding of non-binary codes

En esta tesis se estudia el dise¿no de decodificadores no-binarios para la correcci'on de errores en sistemas de comunicaci'on modernos de alta velocidad. El objetivo es proponer soluciones de baja complejidad para los algoritmos de decodificaci'on basados en los c'odigos de comprobaci'on de paridad de baja densidad no-binarios (NB-LDPC) y en los c'odigos Reed-Solomon, con la finalidad de implementar arquitecturas hardware eficientes. En la primera parte de la tesis se analizan los cuellos de botella existentes en los algoritmos y en las arquitecturas de decodificadores NB-LDPC y se proponen soluciones de baja complejidad y de alta velocidad basadas en el volteo de s'¿mbolos. En primer lugar, se estudian las soluciones basadas en actualizaci'on por inundaci 'on con el objetivo de obtener la mayor velocidad posible sin tener en cuenta la ganancia de codificaci'on. Se proponen dos decodificadores diferentes basados en clipping y t'ecnicas de bloqueo, sin embargo, la frecuencia m'axima est'a limitada debido a un exceso de cableado. Por este motivo, se exploran algunos m'etodos para reducir los problemas de rutado en c'odigos NB-LDPC. Como soluci'on se propone una arquitectura basada en difusi'on parcial para algoritmos de volteo de s'¿mbolos que mitiga la congesti'on por rutado. Como las soluciones de actualizaci 'on por inundaci'on de mayor velocidad son sub-'optimas desde el punto de vista de capacidad de correci'on, decidimos dise¿nar soluciones para la actualizaci'on serie, con el objetivo de alcanzar una mayor velocidad manteniendo la ganancia de codificaci'on de los algoritmos originales de volteo de s'¿mbolo. Se presentan dos algoritmos y arquitecturas de actualizaci'on serie, reduciendo el 'area y aumentando de la velocidad m'axima alcanzable. Por 'ultimo, se generalizan los algoritmos de volteo de s'¿mbolo y se muestra como algunos casos particulares puede lograr una ganancia de codificaci'on cercana a los algoritmos Min-sum y Min-max con una menor complejidad. Tambi'en se propone una arquitectura eficiente, que muestra que el 'area se reduce a la mitad en comparaci'on con una soluci'on de mapeo directo. En la segunda parte de la tesis, se comparan algoritmos de decodificaci'on Reed- Solomon basados en decisi'on blanda, concluyendo que el algoritmo de baja complejidad Chase (LCC) es la soluci'on m'as eficiente si la alta velocidad es el objetivo principal. Sin embargo, los esquemas LCC se basan en la interpolaci'on, que introduce algunas limitaciones hardware debido a su complejidad. Con el fin de reducir la complejidad sin modificar la capacidad de correcci'on, se propone un esquema de decisi'on blanda para LCC basado en algoritmos de decisi'on dura. Por 'ultimo se dise¿na una arquitectura eficiente para este nuevo esquemaGarcía Herrero, FM. (2013). Architectures for soft-decision decoding of non-binary codes [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/33753TESISPremiad

Architecture for time or transform domain decoding of reed-solomon codes

Two pipeline (255,233) RS decoders, one a time domain decoder and the other a transform domain decoder, use the same first part to develop an errata locator polynomial .tau.(x), and an errata evaluator polynominal A(x). Both the time domain decoder and transform domain decoder have a modified GCD that uses an input multiplexer and an output demultiplexer to reduce the number of GCD cells required. The time domain decoder uses a Chien search and polynomial evaluator on the GCD outputs .tau.(x) and A(x), for the final decoding steps, while the transform domain decoder uses a transform error pattern algorithm operating on .tau.(x) and the initial syndrome computation S(x), followed by an inverse transform algorithm in sequence for the final decoding steps prior to adding the received RS coded message to produce a decoded output message