Global Teamwork: A Study of Design Learning in Collaborative Virtual Environments

With the recent developments in communication and information technologies, using Collaborative Virtual Environments (CVEs) in design activity has experienced a remarkable increase. In this paper we present a collaborative learning activity between the University of Sydney (USYD), and the Istanbul Technical University (ITU). This paper shares our teaching experience and discusses the principles of collaborative design learning in virtual environments. Followed by a study on students’ perception on the courses and collaborative learning in both universities, this paper also suggests future refinements on the course structure and the main areas of collaborative design learning. Keywords: Collaborative Design; Collaborative Virtual Environments; Design Teaching And Learning</p

Silicon compilation

Silicon compilation is a term used for many different purposes. In this paper we define silicon compilation as a mapping from some higher level description into layout. We define the basic issues in structural and behavioral silicon compilation and some possible solutions to those issues. Finally, we define the concept of an intelligent silicon compiler in which the compiler evaluates the quality of the generated design and attempts to improve it if it is not satisfactory

PALS/PRISM Software Design Description (SDD): Ver. 0.51

This Software Design Description (SDD) provides detailed information on the architecture and coding for the PRISM C++ library (version 0.51). The PRISM C++ library supports consistent information sharing and in- teractions between distributed components of networked embedded systems, e.g. avionics. It is designed to reduce the complexity of the networked sys- tem by employing synchronous semantics provided by the architectural pat- tern called a Physically-Asynchronous Logically-Synchronous (PALS) system.unpublishednot peer reviewe

Architectural impact of FDDI network on scheduling hard real-time traffic

The architectural impact on guaranteeing synchronous message deadlines in FDDI (Fiber Distributed Data Interface) token ring networks is examined. The FDDI network does not have facility to support (global) priority arbitration which is a useful facility for scheduling hard real time activities. As a result, it was found that the worst case utilization of synchronous traffic in an FDDI network can be far less than that in a centralized single processor system. Nevertheless, it is proposed and analyzed that a scheduling method can guarantee deadlines of synchronous messages having traffic utilization up to 33 pct., the highest to date

Historical awareness support and its evaluation in collaborative software engineering

The types of awareness relevant to collaborative soft- ware engineering are identified and an additional type, "historical awareness" is proposed. This new type of awareness is the knowledge of how software artefacts re- sulting from collaboration have evolved in the course of their development. The types of awareness that different software engineer- ing environment architectures can support are discussed. A way to add awareness support to our existing OSCAR sys- tem, a component of the GENESIS software engineering platform, is proposed. Finally ways of instrumenting and evaluating the awareness support offered by the modified system are outlined

The Design of a System Architecture for Mobile Multimedia Computers

This chapter discusses the system architecture of a portable computer, called Mobile Digital Companion, which provides support for handling multimedia applications energy efficiently. Because battery life is limited and battery weight is an important factor for the size and the weight of the Mobile Digital Companion, energy management plays a crucial role in the architecture. As the Companion must remain usable in a variety of environments, it has to be flexible and adaptable to various operating conditions. The Mobile Digital Companion has an unconventional architecture that saves energy by using system decomposition at different levels of the architecture and exploits locality of reference with dedicated, optimised modules. The approach is based on dedicated functionality and the extensive use of energy reduction techniques at all levels of system design. The system has an architecture with a general-purpose processor accompanied by a set of heterogeneous autonomous programmable modules, each providing an energy efficient implementation of dedicated tasks. A reconfigurable internal communication network switch exploits locality of reference and eliminates wasteful data copies

VLSI Architecture and Design

Integrated circuit technology is rapidly approaching a state where feature sizes of one micron or less are tractable. Chip sizes are increasing slowly. These two developments result in considerably increased complexity in chip design. The physical characteristics of integrated circuit technology are also changing. The cost of communication will be dominating making new architectures and algorithms both feasible and desirable. A large number of processors on a single chip will be possible. The cost of communication will make designs enforcing locality superior to other types of designs. Scaling down feature sizes results in increase of the delay that wires introduce. The delay even of metal wires will become significant. Time tends to be a local property which will make the design of globally synchronous systems more difficult. Self-timed systems will eventually become a necessity. With the chip complexity measured in terms of logic devices increasing by more than an order of magnitude over the next few years the importance of efficient design methodologies and tools become crucial. Hierarchical and structured design are ways of dealing with the complexity of chip design. Structered design focuses on the information flow and enforces a high degree of regularity. Both hierarchical and structured design encourage the use of cell libraries. The geometry of the cells in such libraries should be parameterized so that for instance cells can adjust there size to neighboring cells and make the proper interconnection. Cells with this quality can be used as a basis for "Silicon Compilers"