A survey of emerging architectural techniques for improving cache energy consumption

The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity between the CPU performance and storage. There are encouraging breakthroughs in enhancing CPU performance through fabrication technologies and changes in chip designs but not as much luck has been struck with regards to the computer storage resulting in material negative system performance. A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures. This work is a survey of energy saving techniques which are grouped on whether they save the dynamic energy, leakage energy or both. Needless to mention, the aim of this work is to compile a quick reference guide of energy saving techniques from 2013 to 2016 for engineers, researchers and students

Low power memory allocation and mapping for area-constrained systems-on-chips

Large fractions of today’s embedded systems’ power consumption can be attributed to the memory subsystem. In order to reduce this fraction, we propose a mathematical model to optimize on-chip memory configurations for minimal power. We exploit the power reduction effect of splitting memory into subunits with frequently accessed addresses mapped to small memories. The definition of an integer linear programming model enables us to solve the twofold problem of allocating an optimal set of memory instances with varying size on the one hand and finding an optimal mapping of application segments to allocated memories on the other hand. Experimental results yield power reductions of up to 82 % for instruction memory and 73 % for data memory. Area usage, at the same time, deteriorates by only 2.1 %, respectively, 1.2 % on average and even improves in some cases. Flexibility and performance of our model make it a valuable tool for low power system-on-chip design, either for efficient design space exploration or as part of a HW/SW codesign synthesis flow

Multi-criteria optimization for energy-efficient multi-core systems-on-chip

The steady down-scaling of transistor dimensions has made possible the evolutionary progress leading to today’s high-performance multi-GHz microprocessors and core based System-on-Chip (SoC) that offer superior performance, dramatically reduced cost per function, and much-reduced physical size compared to their predecessors. On the negative side, this rapid scaling however also translates to high power densities, higher operating temperatures and reduced reliability making it imperative to address design issues that have cropped up in its wake. In particular, the aggressive physical miniaturization have increased CMOS fault sensitivity to the extent that many reliability constraints pose threat to the device normal operation and accelerate the onset of wearout-based failures. Among various wearout-based failure mechanisms, Negative biased temperature instability (NBTI) has been recognized as the most critical source of device aging. The urge of reliable, low-power circuits is driving the EDA community to develop new design techniques, circuit solutions, algorithms, and software, that can address these critical issues. Unfortunately, this challenge is complicated by the fact that power and reliability are known to be intrinsically conflicting metrics: traditional solutions to improve reliability such as redundancy, increase of voltage levels, and up-sizing of critical devices do contrast with traditional low-power solutions, which rely on compact architectures, scaled supply voltages, and small devices. This dissertation focuses on methodologies to bridge this gap and establishes an important link between low-power solutions and aging effects. More specifically, we proposed new architectural solutions based on power management strategies to enable the design of low-power, aging aware cache memories. Cache memories are one of the most critical components for warranting reliable and timely operation. However, they are also more susceptible to aging effects. Due to symmetric structure of a memory cell, aging occurs regardless of the fact that a cell (or word) is accessed or not. Moreover, aging is a worst-case matric and line with worst-case access pattern determines the aging of the entire cache. In order to stop the aging of a memory cell, it must be put into a proper idle state when a cell (or word) is not accessed which require proper management of the idleness of each atomic unit of power management. We have proposed several reliability management techniques based on the idea of cache partitioning to alleviate NBTI-induced aging and obtain joint energy and lifetime benefits. We introduce graceful degradation mechanism which allows different cache blocks into which a cache is partitioned to age at different rates. This implies that various sub-blocks become unreliable at different times, and the cache keeps functioning with reduced efficiency. We extended the capabilities of this architecture by integrating the concept of reconfigurable caches to maintain the performance of the cache throughout its lifetime. By this strategy, whenever a block becomes unreliable, the remaining cache is reconfigured to work as a smaller size cache with only a marginal degradation of performance. Many mission-critical applications require guaranteed lifetime of their operations and therefore the hardware implementing their functionality. Such constraints are usually enforced by means of various reliability enhancing solutions mostly based on redundancy which are not energy-friendly. In our work, we have proposed a novel cache architecture in which a smart use of cache partitions for redundancy allows us to obtain cache that meet a desired lifetime target with minimal energy consumption

Energy-efficient memories for wireless sensor networks

Wireless sensor networks (WSNs) embed computation and sensing in the physical world, enabling an unprecedented spectrum of applications in several fields of daily life, such as environmental monitoring, cattle management, elderly care, and medicine to name a few. A WSN comprises sensor nodes, which represents a new class of networked embedded computer characterized by severe resource constraints. The design of a sensor node presents many challenges, as they are expected to be small, reliable, low cost, and low power, since they are powered from batteries or harvest energy from the surrounding environment. In a sensor node, the instantaneous power of the transceiver is usually several orders of magnitude higher than processing power. Nevertheless, if average power is considered in actual applications, the communication energy is only about two times higher than the processing energy. The scaling of CMOS technology provides higher performance at lower prices, enabling more refined distributed applications with augmented local processing. The increased complexity of applications demands for enlarged memory size, which in turn increases the power drain. This scenario becomes even worse as leakage power is becoming more and more important in small feature transistor sizes. In this work the energy consumption of a sensor node is characterized, and different memory architectures were investigated to be integrated in future wireless sensor networks, showing that SRAM memories with sleep state may benefit from low duty-cycle operating system. SRAM memory with power-manageable banks puts idle banks in sleep state to further reduce the leakage power, even when the system is active. Although it is a well known technique, the energy savings limits were not exhaustively stated, nor the inuence of the power management strategy adopted. We proposed a novel and detailed model of the energy saving for uniform banks with two power management schemes: a best-oracle policy and a simple greedy policy. Our model gives valuable insight into key factors (coming from the system and the workload) that are critical for reaching the maximum achievable energy saving. Thanks to our modeling, at design time a near optimum number of banks can be estimated to reach more aggressive energy savings. The memory content allocation problem was solved by an integer linear program formulation. In the framework of this thesis, experiments were carried out for two real wireless sensor network application (based on TinyOS and ContikiOS). Results showed energy reduction close to 80% for a partition overhead of 1% with a memory of ten banks for an application under high workload. Energy saving depends on the access patterns to memory and memory parameters (such as number of banks, partitioning overhead, energy reduction of the sleep state and the wake-up energy cost). The energy saving drops for low duty-cycles. However, a very significant reduction of energy can be achieved, for example, roughly 50% for a 3% duty-cycle operation using the above memory. Finally, our findings suggest that adopting an advanced power management must be carefully evaluated, since the best-oracle is only marginally better than a greedy policy.Las redes de sensores inalámbricas (RSI o WSN, por sus siglas en inglés) agregan computación y sensado al mundo fìsico, posibilitando un rango de aplicaciones sin precedentes en muchos campos de la vida cotidiana, como por ejemplo monitoreo ambiental, manejo de ganado, cuidado de personas adultas mayores y medicina, solo por mencionar algunas. Una RSI consta de nodos sensores, los cuales representan un nuevo tipo de computadora embebida en red, caracterizada por tener grandes restricciones de recursos. El diseño de un nodo sensor presenta muchos desafìos, ya que es necesario que sean, pequeños, confiables, de bajo costo y con muy bajo consumo de energía, ya que se alimentan de pilas o recolectan energía del medio. En un nodo sensor, la potencia instantánea del transceptor (radio) es usualmente algunos órdenes de magnitud mayor que la potencia de procesamiento. Sin embargo, la energía de comunicación es solamente dos veces mayor que la energía de procesamiento. Por otro lado, el escalado de la tecnología CMOS permite mayor performance a menores precios, posibilitando aplicaciones distribuídas más refinadas con más procesamiento local. El aumento de la complejidad de las aplicaciones requiere memorias de mayor tamaño, que a su vez aumenta el consumo de potencia. Este escenario empeora ya que las corrientes de fuga son cada vez más importantes en transistores de menor tamaño. En el presente trabajo de tesis se caracteriza el consumo de energía de un nodo sensor, y se investigan diferentes arquitecturas de memoria para ser integrado en las RSI futuras, mostrando como las memorias SRAM con un estado de sleep pueden ser convenientes en sistemas que operan con bajos ciclos de trabajo. Si además la memoria se divide en bancos que pueden ser controlados de manera independiente, se pueden poner los bancos inactivos en estado sleep, incluso cuando el sistema está activo. Aunque esta es una técnica conocida, los límites de ahorro de energía no habían sido exhaustivamente determinados, ni tampoco la influencia de la política de gestión de energía usado. Se propone un nuevo modelo detallado del ahorro de energía para bancos uniformes con dos políticas de gestión: best-oracle y greedy. Nuestro modelo proporciona información valiosa de los factores fundamentales (provenientes del sistema y la carga de trabajo) que son escenciales para alcanzar el máximo ahorro alcanzable. Gracias a nuestro modelado, en tiempo de diseño se puede estimar el número óptimo de bancos para lograr grandes ahorros de energía. El problema de asignación del código a los bancos fue resuelto usando programación lineal entera. En el contexto de esta tesis, se realizaron experimentos usando dos aplicaciones reales de redes de sensores inalámbricas (basadas en TinyOS y ContikiOS). Los resultados mostraron una reducción de energía cercano a 80% para un overhead de partición de 1% con una memoria de diez bancos para una aplicación con gran carga. El ahorro depende del patrón de acceso a memoria y los parámetros de la memoria (tales como cantidad de bancos, overhead de partición, reducción de energía del estado sleep y el costo energético de wake-up. El ahorro de energía decrece para ciclos de trabajo bajos. Sin embargo, igualmente se alcanzan ahorros de energía significativos, por ejemplo, aproximadamente 50% para ciclos de trabajo de 3% usando la memoria anterior. Finalmente, nuestros resultados sugieren que debe ser cuidadosamente evaluado el uso de políticas de gestón de energía avanzados, ya que la política best-oracle es sólo marginalmente mejor que la política greedy