The design of active resistors and transductors in a CMOS technology

Merged with duplicate record 10026.1/2618 on 07.20.2017 by CS (TIS)This thesis surveys linearisation techniques for implementing monolithic MOS active resistors and transconductors, and investigates the design of linear tunable resistors and transconductors. Improving linearity and tunability in the presence of non-ideal factors such as bulk modulation, mobility-degradation effects and mismatch of transistors is a principal objective. A family of new non-saturation-mode resistors and two novel saturation-mode transconductors are developed. Where possible, approximate analytical expressions are derived to explain the principles of operation. Performance comparisons of the new structures are made with other well-known circuits and their relative advantages and disadvantages evaluated. Experimental and simulation results are presented which validate the proposed linearisation techniques. It is shown that the proposed family of resistors offers improved linearity whilst the transconductors combine extended tunability with low distortion. Continuous-time filter examples are given to demonstrate the potential of these circuits for application in analogue signal-processing tasks.GEC Plessey Semiconductors, Plymout

A power-scalable variable-length analogue DFT processor for multi-standard wireless transceivers

In the Orthogonal Frequency-Division Multiplexing (OFDM) based transceivers, digital computation of the Discrete Fourier Transform (DFT) is a power hungry process. Reduction in the hardware cost and power consumption is possible by implementing the DFT processor with analogue circuits. This thesis presents the real-time recursive DFT processor. Previously, changing the transform length and scaling the power could only be performed by digital Fast Fourier Transform (FFT) processors. By using the real-time recursive DFT processor, the decimation filter is eliminated. Thus, further reduction in the hardware cost and power consumption of the multi-standard transceiver is achieved. The real-time recursive DFT processor was designed in 180 nm CMOS technology. Results of device mismatch analysis indicate that the 8-point recursive DFT processor has a yield of 97.5% for the BPSK modulated signal. For the QPSK modulated signal, however, yield of the 8-point recursive DFT processor is 8.9%. Moreover, doubling the transform length reduces the average dynamic range by 3dB. Accordingly, the 16-point recursive DFT processor has a yield of 43.4% for the BPSK modulated signal. Power consumption of the recursive DFT processor is about 1/6 of the power consumption of a previous analogue FFT processor

Ultra low power circuits for a miniature apnoea detection device

Imperial Users onl

VLSI Design of Heart Model

Heart disease is a leading cause of death in the United States and abroad. Research interests arise in understanding the nature of the dynamics of the heart and seeking methods to control and suppress arrhythmias. Simulation of the heart electrical activity is a useful approach to study the heart because it yields some quantities of interest that cannot practically be obtained in any other way. However, the complexity of the human heart leads to complicated mathematical models, and consequently, modeling arrhythmias of a whole heart with computers is extremely data intensive and computational challenging. In this dissertation, we introduce an analog VLSI design that simulates cardiac electrical activities. The selected cardiac model is based on the Beeler-Reuter equations and the continuous core-conductor model. The Beeler-Reuter equations formulate the membrane ionic kinetics of ventricular cells, and the core-conductor model describes the electrical signal conduction on cardiac tissues. We discuss the design flows of mapping equations into circuits and present a set of circuit blocks of basic mathematical function units. The transistor circuits for realizing the ionic model of a single cell is introduced, and capacitors are used to calculate time directives. A method of shifting the initial conditions of differential equations to zero is discussed for saving the circuit which sets up the initial voltages of the capacitors. We also introduce a method of implementing reaction-diffusion systems using non-linear RC networks, and present the circuit which simulates the reaction-diffusion process, i.e. the electrical propagation, of the heart. Error analysis is carried out for the circuit-realized Beeler-Reuter model by comparing the simulated functions with the equation calculated values. The PSpice simulation results show that the circuit created action potential is satisfactory. The important reentry phenomena, the primary mechanism underlying fibrillation, is presented, and an anatomical reentry in the 1-dimensional model and a functional reentry (spiral wave) in the 2-dimensional model are successfully simulated in circuits. The presented methods of implementing equations with analog VLSI circuit contribute to the fundamentals for a novel technique of obtaining numerical solutions and potential fast application-specified analog computational devices if the circuits are fabricated on chips. Unlike computing with digital computers, which is mainly a serial process and needs to discretize the space and the time domain for finding numerical solutions of the discretization points one by one, computation with analog VLSI relies on the physics of the electrical devices and takes advantage of the integration properties of capacitors and, hence, computing in analog circuit hardware is a parallel process and can be real-time, that is, the calculation time is the time simulated by equations

Synaptic rewiring in neuromorphic VLSI for topographic map formation

A generalised model of biological topographic map development is presented which combines both weight plasticity and the formation and elimination of synapses (synaptic rewiring) as well as both activity-dependent and -independent processes. The question of whether an activity-dependent process can refine a mapping created by an activity-independent process is investigated using a statistical approach to analysingmapping quality. The model is then implemented in custom mixed-signal VLSI. Novel aspects of this implementation include: (1) a distributed and locally reprogrammable address-event receiver, with which large axonal fan-out does not reduce channel capacity; (2) an analogue current-mode circuit for Euclidean distance calculation which is suitable for operation across multiple chips; (3) slow probabilistic synaptic rewiring driven by (pseudo-)random noise; (4) the application of a very-low-current design technique to improving the stability of weights stored on capacitors; (5) exploiting transistor non-ideality to implement partially weightdependent spike-timing-dependent plasticity; (6) the use of the non-linear capacitance of MOSCAP devices to compensate for other non-linearities. The performance of the chip is characterised and it is shown that the fabricated chips are capable of implementing the model, resulting in biologically relevant behaviours such as activity-dependent reduction of the spatial variance of receptive fields. Complementing a fast synaptic weight change mechanism with a slow synapse rewiring mechanism is suggested as a method of increasing the stability of learned patterns