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Designing an efficient test pattern generator using input reduction with linear operations
Advances in fabrication technology have resulted in more complicated systems, being used in ever increasing numbers of applications. The large increase in transistor counts versus the number of pins on the chip has made VLSI testing much harder than ever before. Denser integrated circuits chips increase the required test cases enormously for comprehensive testing of a chip. This results in expensive test cost and long test time. In this thesis, an improved method for on-chip test pattern generation is proposed. It generates a complete test set more efficiently by using input reduction with linear operations. Input reduction for pseudo-exhaustive test pattern generation based on compatible and inverse-compatible relationships between inputs has been proposed in the past. This work extends the concept by using linear combinations of inputs to generate other inputs as a means for further input reduction. Results are presented showing the improvements that can be obtained.Electrical and Computer Engineerin
Construction of Neural Network Classification Expert Systems Using Switching Theory Algorithms
A new family of neural network architectures is presented. This family of architectures solves the problem of constructing and training minimal neural network classification expert systems by using switching theory. The primary insight that leads to the use of switching theory is that the problem of minimizing the number of rules and the number of IF statements (antecedents) per rule in a neural network expert system can be recast into the problem of minimizing the number of digital gates and the number of connections between digital gates in a Very Large Scale Integrated (VLSI) circuit. The rules that the neural network generates to perform a task are readily extractable from the network's weights and topology. Analysis and simulations on the Mushroom database illustrate the system's performance
Automatic March tests generation for static and dynamic faults in SRAMs
New memory production modern technologies introduce new classes of faults usually referred to as dynamic memory faults. Although some hand-made March tests to deal with these new faults have been published, the problem of automatically generate March tests for dynamic faults has still to be addressed, in this paper we propose a new approach to automatically generate March tests with minimal length for both static and dynamic faults. The proposed approach resorts to a formal model to represent faulty behaviors in a memory and to simplify the generation of the corresponding tests
March Test Generation Revealed
Memory testing commonly faces two issues: the characterization of detailed and realistic fault models and the definition of time-efficient test algorithms. Among the different types of algorithms proposed for testing static random access memories, march tests have proven to be faster, simpler, and regularly structured. The majority of the published march tests have been manually generated. Unfortunately, the continuous evolution of the memory technology introduces new classes of faults such as dynamic and linked faults and makes the task of handwriting test algorithms harder and not always leading to optimal results. Although some researchers published handmade march tests able to deal with new fault models, the problem of a comprehensive methodology to automatically generate march tests addressing both classic and new fault models is still an open issue. This paper proposes a new polynomial algorithm to automatically generate march tests. The formal model adopted to represent memory faults allows the definition of a general methodology to deal with static, dynamic, and linked faults. Experimental results show that the new automatically generated march tests reduce the test complexity and, therefore, the test time, compared to the well-known state of the art in memory testin
Testability enhancement of a basic set of CMOS cells
Testing should be evaluated as the ability of the test patterns to cover realistic faults, and high quality IC products demand high quality testing. We use a test strategy based on physical design for testability (to discover both open and short faults, which are difficult or even impossible to detect). Consequentially, layout level design for testability (LLDFT) rules have been developed, which prevent the faults, or at least reduce the chance of their appearing. The main purpose of this work is to apply a practical set of LLDFT rules to the library cells designed by the Centre Nacional de MicroelectrĂČnica (CNM) and obtain a highly testable cell library. The main results of the application of the LLDFT rules (area overheads and performance degradation) are summarized and the results are significant since IC design is highly repetitive; a small effort to improve cell layout can bring about great improvement in design
A method for developing design diagrams for ceramic and glass materials using fatigue data
The service lifetime of glass and ceramic materials can be expressed as a plot of time-to-failure versus applied stress whose plot is parametric in percent probability of failure. This type of plot is called a design diagram. Confidence interval estimates for such plots depend on the type of test that is used to generate the data, on assumptions made concerning the statistical distribution of the test results, and on the type of analysis used. This report outlines the development of design diagrams for glass and ceramic materials in engineering terms using static or dynamic fatigue tests, assuming either no particular statistical distribution of test results or a Weibull distribution and using either median value or homologous ratio analysis of the test results
Memory Fault Simulator for Static-Linked Faults
Static linked faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and makes test algorithm design and validation a very complex task. This paper presents a memory fault simulator architecture targeting the full set of linked fault
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