Application of a new interconnection technology for the ATLAS pixel upgrade at SLHC

We present an R&D activity aiming towards a new detector concept in the framework of the ATLAS pixel detector upgrade exploiting a vertical integration technology developed at the Fraunhofer Institute IZMMunich. The Solid-Liquid InterDiffusion (SLID) technique is investigated as an alternative to the bump-bonding process. We also investigate the extraction of the signals from the back of the read-out chip through Inter-Chip-Vias to achieve a higher fraction of active area with respect to the present ATLAS pixel module. We will present the layout and the first results obtained with a production of test-structures designed to investigate the SLID interconnection efficiency as a function of different parameters, i.e. the pixel size and pitch, as well as the planarity of the underlying layers

Low mass hybrid pixel detectors for the high luminosity LHC upgrade

Reducing material in silicon trackers is of major importance for a good overall detector performance, and poses severe challenges to the design of the tracking system. To match the low mass constraints for trackers in High Energy Physics experiments at high luminosity, dedicated technological developments are required. This dissertation presents three technologies to design low mass hybrid pixel detectors for the high luminosity upgrades of the LHC. The work targets specifically the reduction of the material from the detector services and modules, with novel powering schemes, flip chip and interconnection technologies. A serial powering scheme is prototyped, featuring a new regulator concept, a control and protection element, and AC-coupled data transmission. A modified flip chip technology is developed for thin, large area Front-End chips, and a via last Through Silicon Via process is demonstrated on existing pixel modules. These technologies, their developments, and the achievable material reduction are discussed using the upgrades of the ATLAS pixel detector as a case study

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities

Application of the SLID-ICV interconnection technology for the ATLAS pixel upgrade at SLHC

The presented R&D activity is focused on the development of a new detector for the upgrade of the ATLAS pixel system at SLHC at CERN, Geneva, employing thin pixel sensors together with a novel vertical integration technology. It consists of the Solid-Liquid-InterDiffusion (SLID) interconnection, which is an alternative to the standard solder bump-bonding, and Inter Chip Vias (ICV) for routing the signal vertically through the readout chips. The SLID interconnection is characterized by a very thin eutectic Cu-Sn alloy, achieved through the deposition of 5 m of Cu on both sides, and 3 m of Sn on one side only. The thin pixels are connected by the SLID process to the read out ASICs in the "chip to wafer" approach using tested known good dies. The inter chip vias are placed in the r/o chips before the SLID process in the "via last" approach. This approach gives the highest flexibility for the choice of the sensor and ASIC technology. The best possible sensors can be produce d in a highly specialized technology on a dedicated process line and then in subsequent post-processing bonded to r/o ASICs coming from a standard CMOS line