Alternative Methods for Non-Linearity Estimation in High-Resolution Analog-to-Digital Converters

The evaluation of the linearity performance of a high resolution Analog-to- Digital Converter (ADC) by the Standard Histogram method is an outstanding challenge due to the requirement of high purity of the input signal and the high number of output data that must be acquired to obtain an acceptable accuracy on the estimation. These requirements become major application drawbacks when the measures have to be performed multiple times within long test flows and for many parts, and under an industrial environment that seeks to reduce costs and lead times as is the case in the New Space sector. This thesis introduces two alternative methods that succeed in relaxing the two previous requirements for the estimation of the Integral Nonlinearity (INL) parameter in ADCs. The methods have been evaluated by estimating the Integral Non-Linearity pattern by simulation using realistic high-resolution ADC models and experimentally by applying them to real high performance ADCs. First, the challenge of applying the Standard Histogram method for the evaluation of static parameters in high resolution ADCs and how the drawbacks are accentuated in the New Space industry is analysed, being a highly expensive method for an industrial environment where cost and lead time reduction is demanded. Several alternative methods to the Standard Histogram for estimating Integral Nonlinearity in high resolution ADCs are reviewed and studied. As the number of existing works in the literature is very large and addressing all of them is a challenge in itself, only those most relevant to the development of this thesis have been included. Methods based on spectral processing to reduce the number of data acquired for the linearity test and methods based on a double histogram to be able to use generators that do not meet the the purity requirement against the ADC to be tested are further analysed. Two novel contributions are presented in this work for the estimation of the Integral Nonlinearity in ADCs, as possible alternatives to the Standard Histogram method. The first method, referred to as SSA (Simple Spectral Approach), seeks to reduce the number of output data that need to be acquired and focuses on INL estimation using an algorithm based on processing the spectrum of the output signal when a sinusoidal input stimulus is used. This type of approach requires a much smaller number of samples than the Standard Histogram method, although the estimation accuracy will depend on how smooth or abrupt the ADC nonlinearity pattern is. In general, this algorithm cannot be used to perform a calibration of the ADC nonlinearity error, but it can be applied to find out between which limits it lies and what its approximate shape is. The second method, named SDH (Simplified Double Histogram)aims to estimate the Non-Linearity of the ADC using a poor linearity generator. The approach uses two histograms constructed from the two set of output data in response to two identical input signals except for a dc offset between them. Using a simple adder model, an extended approach named ESDH (Extended Simplified Double Histogram) addresses and corrects for possible time drifts during the two data acquisitions, so that it can be successfully applied in a non-stationary test environment. According to the experimental results obtained, the proposed algorithm achieves high estimation accuracy. Both contributions have been successfully tested in high-resolution ADCs with both simulated and real laboratory experiments, the latter using a commercial ADC with 14-bit resolution and 65Msps sampling rate (AD6644 from Analog Devices).La medida de la característica de linealidad de un convertidor analógicodigital (ADC) de alta resolución mediante el método estándar del Histograma constituye un gran desafío debido los requisitos de alta pureza de la señal de entrada y del elevado número de datos de salida que deben adquirirse para obtener una precisión aceptable en la estimación. Estos requisitos encuentran importantes inconvenientes para su aplicación cuando las medidas deben realizarse dentro de largos flujos de pruebas, múltiples veces y en un gran número de piezas, y todo bajo un entorno industrial que busca reducir costes y plazos de entrega como es el caso del sector del Nuevo Espacio. Esta tesis introduce dos métodos alternativos que consiguen relajar los dos requisitos anteriores para la estimación de los parámetros de no linealidad en los ADCs. Los métodos se han evaluado estimando el patrón de No Linealidad Integral (INL) mediante simulación utilizando modelos realistas de ADC de alta resolución y experimentalmente aplicándolos en ADCs reales. Inicialmente se analiza el reto que supone la aplicación del método estándar del Histograma para la evaluación de los parámetros estáticos en ADCs de alta resolución y cómo sus inconvenientes se acentúan en la industria del Nuevo Espacio, siendo un método altamente costoso para un entorno industrial donde se exige la reducción de costes y plazos de entrega. Se estudian métodos alternativos al Histograma estándar para la estimación de la No Linealidad Integral en ADCs de alta resolución. Como el número de trabajos es muy amplio y abordarlos todos es ya en sí un desafío, se han incluido aquellos más relevantes para el desarrollo de esta tesis. Se analizan especialmente los métodos basados en el procesamiento espectral para reducir el número de datos que necesitan ser adquiridos y los métodos basados en un doble histograma para poder utilizar generadores que no cumplen el requisito de precisión frente al ADC a medir. En este trabajo se presentan dos novedosas aportaciones para la estimación de la No Linealidad Integral en ADCs, como posibles alternativas al método estándar del Histograma. El primer método, denominado SSA (Simple Spectral Approach), busca reducir el número de datos de salida que es necesario adquirir y se centra en la estimación de la INL mediante un algoritmo basado en el procesamiento del espectro de la señal de salida cuando se utiliza un estímulo de entrada sinusoidal. Este tipo de enfoque requiere un número mucho menor de muestras que el método estándar del Histograma, aunque la precisión de la estimación dependerá de lo suave o abrupto que sea el patrón de no-linealidad del ADC a medir. En general, este algoritmo no puede utilizarse para realizar una calibración del error de no linealidad del ADC, pero puede aplicarse para averiguar entre qué límites se encuentra y cuál es su forma aproximada. El segundo método, denominado SDH (Simplified Double Histogram) tiene como objetivo estimar la no linealidad del ADC utilizando un generador de baja pureza. El algoritmo utiliza dos histogramas, construidos a partir de dos conjuntos de datos de salida en respuesta a dos señales de entrada idénticas, excepto por un desplazamiento constante entre ellas. Utilizando un modelo simple de sumador, un enfoque ampliado denominado ESDH (Extended Simplified Double Histogram) aborda y corrige las posibles derivas temporales durante las dos adquisiciones de datos, de modo que puede aplicarse con éxito en un entorno de prueba no estacionario. De acuerdo con los resultados experimentales obtenidos, el algoritmo propuesto alcanza una alta precisión de estimación. Ambas contribuciones han sido probadas en ADCs de alta resolución con experimentos tanto simulados como reales en laboratorio, estos últimos utilizando un ADC comercial con una resolución de 14 bits y una tasa de muestreo de 65Msps (AD6644 de Analog Devices)

Design and demonstration of digital pre-distortion using software defined radio

Abstract. High data rates for large number of users set tight requirements for signal quality measured in terms of error vector magnitude (EVM). In radio transmitters, nonlinear distortion dominated by power amplifiers (PAs) often limits the achievable EVM. However, the linearity can be improved by linearization techniques. Digital pre-distortion (DPD) is one of these widely used linearization techniques for an effective distortion reduction over a wide bandwidth. In DPD, the nonlinearity of the transmitter is pre-compensated in the digital domain to achieve linear output. Moreover, DPD is used to enable PAs to operate in the power-efficient region with a decent linearity. As we are moving towards millimetre-wave frequencies to enable the wideband communications, the design of the DPD algorithm must be optimized in terms of performance and power consumption. Moreover, continuous development of wireless infrastructure motivates to make research on programmable and reconfigurable platforms in order to decrease the demonstration cost and time, especially for the demonstration purposes. This thesis illustrates and presents how software defined radio (SDR) platforms can be used to demonstrate DPD. Universal software defined peripheral (USRP) X300 is a commercial software defined radio (SDR) platform. The chosen model, X300, has two independent channels equipped with individual transceiver cards. SIMULINK is used to communicate with the device and the two channels of X300 are used as transmitter and receiver simultaneously in full-duplex mode. Hence, a single USRP device is acting as an operational transmitter and feedback receiver, simultaneously. The implemented USRP design consists of SIMULINK based transceiver design and lookup table based DPD in which the coefficients are calculated in MATLAB offline. An external PA, i.e. ZFL-2000+ together with a directional coupler and attenuator are connected between the TX/RX port and RX2 port to measure the nonlinearity. The nonlinearity transceiver is measured with and without the external PA. The experimental results show decent performance for linearization by using the USRP platform. However, the results differ widely due to the used USRP transceiver parameterization and PA operational point. The 16 QAM test signal with 500 kHz bandwidth is fed to the USRP transmit chain. As an example, the DPD algorithm improves the EVM from 7.6% to 2.1% and also the ACPR is reduced around 10 dB with the 16 QAM input signal where approximately + 2.2 dBm input power applied to the external PA

Design of a Cost-Efficient Reconfigurable Pipeline ADC

Power budget is very critical in the design of battery-powered implantable biomedical instruments. High speed, high resolution and low power usually cannot be achieved at the same time. Therefore, a tradeoff must be made to compromise every aspect of those features. As the main component of the bioinstrument, high conversion rate, high resolution ADC consumes most of the power. Fortunately, based on the operation modes of the bioinstrument, a reconfigurable ADC can be used to solve this problem. The reconfigurable ADC will operate at 10-bit 40 MSPS for the diagnosis mode and at 8-bit 2.5 MSPS for the monitor mode. The ADC will be completely turned off if no active signal comes from sensors or if an off command is received from the antenna. By turning off the sample hold stage and the first two stages of the pipeline ADC, a significant power saving is achieved. However, the reconfigurable ADC suffers from two drawbacks. First, the leakage signals through the extra off-state switches in the third stage degrade the performance of the data converter. This situation tends to be even worse for high speed and high-resolution applications. An interference elimination technique has been proposed in this work to solve this problem. Simulation results show a significant attenuation of the spurious tones. Moreover, the transistors in the OTA tend to operate in weak inversion region due to the scaling of the bias current. The transistor in subthreshold is very slow due to the small transit frequency. In order to get a better tradeoff between the transconductance efficiency and the transit frequency, reconfigurable OTAs and scalable bias technique are devised to adjust the operating point from weak inversion to moderate inversion. The figure of merit of the reconfigurable ADC is comparable to the previously published conventional pipeline ADCs. For the 10-bit, 40 MSPS mode, the ADC attains a 56.9 dB SNDR for 35.4 mW power consumption. For the 8-bit 2.5 MSPS mode, the ADC attains a 49.2 dB SNDR for 7.9 mW power consumption. The area for the core layout is 1.9 mm2 for a 0.35 micrometer process

Towards low-cost gigabit wireless systems at 60 GHz

The world-wide availability of the huge amount of license-free spectral space in the 60 GHz band provides wide room for gigabit-per-second (Gb/s) wireless applications. A commercial (read: low-cost) 60-GHz transceiver will, however, provide limited system performance due to the stringent link budget and the substantial RF imperfections. The work presented in this thesis is intended to support the design of low-cost 60-GHz transceivers for Gb/s transmission over short distances (a few meters). Typical applications are the transfer of high-definition streaming video and high-speed download. The presented work comprises research into the characteristics of typical 60-GHz channels, the evaluation of the transmission quality as well as the development of suitable baseband algorithms. This can be summarized as follows. In the first part, the characteristics of the wave propagation at 60 GHz are charted out by means of channel measurements and ray-tracing simulations for both narrow-beam and omni-directional configurations. Both line-of-sight (LOS) and non-line-of-sight (NLOS) are considered. This study reveals that antennas that produce a narrow beam can be used to boost the received power by tens of dBs when compared with omnidirectional configurations. Meanwhile, the time-domain dispersion of the channel is reduced to the order of nanoseconds, which facilitates Gb/s data transmission over 60-GHz channels considerably. Besides the execution of measurements and simulations, the influence of antenna radiation patterns is analyzed theoretically. It is indicated to what extent the signal-to-noise ratio, Rician-K factor and channel dispersion are improved by application of narrow-beam antennas and to what extent these parameters will be influenced by beam pointing errors. From both experimental and analytical work it can be concluded that the problem of the stringent link-budget can be solved effectively by application of beam-steering techniques. The second part treats wideband transmission methods and relevant baseband algorithms. The considered schemes include orthogonal frequency division multiplexing (OFDM), multi-carrier code division multiple access (MC-CDMA) and single carrier with frequency-domain equalization (SC-FDE), which are promising candidates for Gb/s wireless transmission. In particular, the optimal linear equalization in the frei quency domain and associated implementation issues such as synchronization and channel estimation are examined. Bit error rate (BER) expressions are derived to evaluate the transmission performance. Besides the linear equalization techniques, a low-complexity inter-symbol interference cancellation technique is proposed to achieve much better performance of code-spreading systems such as MC-CDMA and SC-FDE. Both theoretical analysis and simulations demonstrate that the proposed scheme offers great advantages as regards both complexity and performance. This makes it particularly suitable for 60-GHz applications in multipath environments. The third part treats the influence of quantization and RF imperfections on the considered transmission methods in the context of 60-GHz radios. First, expressions for the BER are derived and the influence of nonlinear distortions caused by the digital-to-analog converters, analog-to-digital converters and power amplifiers on the BER performance is examined. Next, the BER performance under the influence of phase noise and IQ imbalance is evaluated for the case that digital compensation techniques are applied in the receiver as well as for the case that such techniques are not applied. Finally, a baseline design of a low-cost Gb/s 60-GHz transceiver is presented. It is shown that, by application of beam-steering in combination with SC-FDE without advanced channel coding, a data rate in the order of 2 Gb/s can be achieved over a distance of 10 meters in a typical NLOS indoor scenario

Digital Power Detector for WCDMA Transmitter

A 3G mobile phone must have the ability to control its output power with high precision. A power detector is used to measure the actual power outputted by the power amplifier to the antenna. With higher data rates the traditional implementations with peak detectors have become very difficult to use, which is why true RMS detectors are needed. In this thesis the digital part of a true RMS detector for W-CDMA has been designed. The analog parts of the power detector form a quadrature demodulator that transforms the radio signal down to DC where it is occupies a band from 0 to 2 MHz. The measured power amplifier output signal is sampled at 1 MHz which prohibits direct calculation of the RMS voltage in the detector. Instead the detector uses the wave form generator output as a reference to determine the amplification in the transmitter chain which can then be used to find the output power (wave form generator output has constant known power). This requires time alignment of the two signals which is done using a least mean square method of correlation. Using the reference up-sampled to 104 MHz allows very good accuracy despite the low sample rate of the power amplifier signal. To overcome distortion in the power amplifier an additional distortion reducing algorithm has been developed. An estimate of the output power can be delivered after 100 μs and has a standard deviation of its error of 0.05 dB. The error from changing modulation type is limited to a maximum 0.04 dB, well below the specified 0.1 dB. The solution is accurate and modulation independent