Hierarchical Up/Down Routing Architecture for Ethernet backbones and campus networks

We describe a new layer two distributed and scalable routing architecture. It uses an automatic hierarchical node identifier assignment mechanism associated to the rapid spanning tree protocol. Enhanced up/down mechanisms are used to prohibit some turns at nodes to break cycles, instead of blocking links like the spannning tree protocol does. The protocol performance is similar or better than other turn prohibition algorithms recently proposed with lower complexity O(Nd) and better scalability. Simulations show that the fraction of prohibited turns over random networks is less than 0.2. The effect of root bridge election on the performance of the protocol is limited both in the random and regular networks studied. The use of hierarchical, tree-descriptive addresses simplifies the routing, and avoids the need of all nodes having a global knowleddge of the network topology. Routing frames through the hierarchical tree at very high speed is possible by progressive decoding of frame destination address, without routing tables or port address learning. Coexistence with standard bridges is achieved using combined devices: bridges that forward the frames having global destination MAC addresses as standard bridges and frames with local MAC frames with the proposed protocol.Publicad

On Cyclic Dependencies and Regulators in Time-Sensitive Networks

For time-sensitive networks, as in the context of IEEE TSN and IETF Detnet, cyclic dependencies are associated with certain fundamental properties such as improving availability and decreasing reconfiguration effort. Nevertheless, the existence of cyclic dependencies can cause very large latency bounds or even global instability, thus making the proof of the timing predictability of such networks a much more challenging issue. Cyclic dependencies can be removed by reshaping flows inside the network, by means of regulators. We consider FIFO-per-class networks with two types of regulators: perflow regulators and interleaved regulators (the latter reshape entire flow aggregates). Such regulators come with a hardware cost that is less for an interleaved regulator than for a perflow regulator; both can affect the latency bounds in different ways. We analyze the benefits of both types of regulators in partial and full deployments in terms of latency. First, we propose Low-Cost Acyclic Network (LCAN), a new algorithm for finding the optimum number of regulators for breaking all cyclic dependencies. Then, we provide another algorithm, Fixed- Point Total Flow Analysis (FP-TFA), for computing end-to-end delay bounds for general topologies, i.e., with and without cyclic dependencies. An extensive analysis of these proposed algorithms was conducted on generic grid topologies. For these test networks, we find that FP-TFA computes small latency bounds; but, at a medium to high utilization, the benefit of regulators becomes apparent. At high utilization or for high line transmission-rates, a small number of per-flow regulators has an effect on the latency bound larger than a small number of interleaved regulators. Moreover, interleaved regulators need to be placed everywhere in the network to provide noticeable improvements. We validate the applicability of our approaches on a realistic industrial timesensitive network

Automatic synthesis and optimization of chip multiprocessors

The microprocessor technology has experienced an enormous growth during the last decades. Rapid downscale of the CMOS technology has led to higher operating frequencies and performance densities, facing the fundamental issue of power dissipation. Chip Multiprocessors (CMPs) have become the latest paradigm to improve the power-performance efficiency of computing systems by exploiting the parallelism inherent in applications. Industrial and prototype implementations have already demonstrated the benefits achieved by CMPs with hundreds of cores.CMP architects are challenged to take many complex design decisions. Only a few of them are:- What should be the ratio between the core and cache areas on a chip?- Which core architectures to select?- How many cache levels should the memory subsystem have?- Which interconnect topologies provide efficient on-chip communication?These and many other aspects create a complex multidimensional space for architectural exploration. Design Automation tools become essential to make the architectural exploration feasible under the hard time-to-market constraints. The exploration methods have to be efficient and scalable to handle future generation on-chip architectures with hundreds or thousands of cores.Furthermore, once a CMP has been fabricated, the need for efficient deployment of the many-core processor arises. Intelligent techniques for task mapping and scheduling onto CMPs are necessary to guarantee the full usage of the benefits brought by the many-core technology. These techniques have to consider the peculiarities of the modern architectures, such as availability of enhanced power saving techniques and presence of complex memory hierarchies.This thesis has several objectives. The first objective is to elaborate the methods for efficient analytical modeling and architectural design space exploration of CMPs. The efficiency is achieved by using analytical models instead of simulation, and replacing the exhaustive exploration with an intelligent search strategy. Additionally, these methods incorporate high-level models for physical planning. The related contributions are described in Chapters 3, 4 and 5 of the document.The second objective of this work is to propose a scalable task mapping algorithm onto general-purpose CMPs with power management techniques, for efficient deployment of many-core systems. This contribution is explained in Chapter 6 of this document.Finally, the third objective of this thesis is to address the issues of the on-chip interconnect design and exploration, by developing a model for simultaneous topology customization and deadlock-free routing in Networks-on-Chip. The developed methodology can be applied to various classes of the on-chip systems, ranging from general-purpose chip multiprocessors to application-specific solutions. Chapter 7 describes the proposed model.The presented methods have been thoroughly tested experimentally and the results are described in this dissertation. At the end of the document several possible directions for the future research are proposed

Exact Worst-case Delay in FIFO-multiplexing Feed-forward Networks

In this paper, we compute the actual worst-case end-to-end delay for a flow in a feed-forward network of first-in–first-out (FIFO)-multiplexing service curve nodes, where flows are shaped by piecewise-affine concave arrival curves, and service curves are piecewise affine and convex. We show that the worst-case delay problem can be formulated as a mixed integer linear programming problem, whose size grows exponentially with the number of nodes involved. Furthermore, we present approximate solution schemes to find upper and lower delay bounds on the worst-case delay. Both only require to solve just one linear programming problem and yield bounds that are generally more accurate than those found in the previous work, which are computed under more restrictive assumptions

Routing in turn-prohibition based feed-forward networks

Abstract. The application of queuing theory to communications systems often requires that the respective networks are of a feed-forward nature, that is they have to be free of cyclic dependencies. An effective way to ensure this property is to identify a certain set of critical turns and to prohibit their use. A turn is a concatenation of two adjacent, consecutive links. Unfortunately, current routing algorithms are usually not equipped to handle forbidden turns and the required extensions are nontrivial. We discuss the relevant issues for the example of the widely deployed Dijkstra algorithm. Then, we address the general case and introduce the Turnnet concept, which supports arbitrary combinations of routing algorithms with turn-prohibiting feed-forward mechanisms

Дослідження та вдосконалення алгоритмів адміністрування мережевої бази даних “Navi”

Робота публікується згідно наказу ректора від 29.12.2020 р. №580/од "Про розміщення кваліфікаційних робіт вищої освіти в репозиторії НАУ". Керівник проекту: к.т.н., доцент Проценко Микола МихайловичLong before the advent of computerized databases, humanity already then had a need to store information in a structured form. Since at a time when computers either did not exist at all, or they were just entering the market and were at the stage of their formation, peculiar databases existed in written or physical form, for example, data archives, reference centers, libraries, ledgers, telephone directories etc. And since now there is a need to store huge amounts of information, while taking up as little storage space and resources as possible, databases are an integral stage in the development of opportunities to simplify the life of mankind. The database is both a tool and the very subject of a collection of data, which shows the state of certain objects and their relationship in a certain subject area.Задовго до появи комп'ютеризованих баз даних людство вже тоді мало потребу зберігати інформацію у структурованому вигляді. Оскільки в той час, коли комп’ютери або взагалі не існували, або вони тільки виходили на ринок і були на стадії свого формування, своєрідні бази даних існували в письмовій або фізичній формі, наприклад, архіви даних, довідкові центри, бібліотеки, книги , телефонні довідники тощо. І оскільки зараз існує потреба зберігати величезні обсяги інформації, займаючи при цьому якомога менше місця для зберігання та ресурсів, бази даних є невід’ємним етапом у розвитку можливостей спрощення життя людства. База даних є одночасно інструментом і самим предметом збору даних, який показує стан певних об’єктів та їх взаємозв’язок у певній предметній області