Shift register generators and applications to coding

The most important properties of shift register generated sequences are exposed. The application of shift registers as multiplication and division circuits leads to the generation of some error correcting and detecting codes

Codes for Asymmetric Limited-Magnitude Errors With Application to Multilevel Flash Memories

Several physical effects that limit the reliability and performance of multilevel flash memories induce errors that have low magnitudes and are dominantly asymmetric. This paper studies block codes for asymmetric limited-magnitude errors over q-ary channels. We propose code constructions and bounds for such channels when the number of errors is bounded by t and the error magnitudes are bounded by ℓ. The constructions utilize known codes for symmetric errors, over small alphabets, to protect large-alphabet symbols from asymmetric limited-magnitude errors. The encoding and decoding of these codes are performed over the small alphabet whose size depends only on the maximum error magnitude and is independent of the alphabet size of the outer code. Moreover, the size of the codes is shown to exceed the sizes of known codes (for related error models), and asymptotic rate-optimality results are proved. Extensions of the construction are proposed to accommodate variations on the error model and to include systematic codes as a benefit to practical implementation

Fault-tolerant computer study

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed

An extensive English language bibliography on graph theory and its applications, supplement 1

Graph theory and its applications - bibliography, supplement

Performance and structure of single-mode bosonic codes

The early Gottesman, Kitaev, and Preskill (GKP) proposal for encoding a qubit in an oscillator has recently been followed by cat- and binomial-code proposals. Numerically optimized codes have also been proposed, and we introduce new codes of this type here. These codes have yet to be compared using the same error model; we provide such a comparison by determining the entanglement fidelity of all codes with respect to the bosonic pure-loss channel (i.e., photon loss) after the optimal recovery operation. We then compare achievable communication rates of the combined encoding-error-recovery channel by calculating the channel's hashing bound for each code. Cat and binomial codes perform similarly, with binomial codes outperforming cat codes at small loss rates. Despite not being designed to protect against the pure-loss channel, GKP codes significantly outperform all other codes for most values of the loss rate. We show that the performance of GKP and some binomial codes increases monotonically with increasing average photon number of the codes. In order to corroborate our numerical evidence of the cat/binomial/GKP order of performance occurring at small loss rates, we analytically evaluate the quantum error-correction conditions of those codes. For GKP codes, we find an essential singularity in the entanglement fidelity in the limit of vanishing loss rate. In addition to comparing the codes, we draw parallels between binomial codes and discrete-variable systems. First, we characterize one- and two-mode binomial as well as multi-qubit permutation-invariant codes in terms of spin-coherent states. Such a characterization allows us to introduce check operators and error-correction procedures for binomial codes. Second, we introduce a generalization of spin-coherent states, extending our characterization to qudit binomial codes and yielding a new multi-qudit code.Comment: 34 pages, 11 figures, 4 tables. v3: published version. See related talk at https://absuploads.aps.org/presentation.cfm?pid=1351

Using of Residual Number System as a Mathematical Basis for Software Defined Radio

Вступ. У традицiйному виглядi, програмно-визначена радiосистема (Software Defined Radio, SDR) являє собою обчислювальне ядро, обладнане приймально-передавальними блоками. З метою прискорення обчислювальних операцiй у системах SDR, пропонується у якостi математичної основи застосування системи залишкових класiв. Результати попереднiх дослiджень, що проводились рiзними групами вчених з метою пошукiв шляхiв пiдвищення продуктивностi обчислювальних засобiв, методiв органiзацiї ефективної системи виявлення та виправлення помилок, а також побудови надiйних обчислювальних комплексiв, дають можливiсть стверджувати, що в межах позицiйних систем числення не можна очiкувати принципових зрушень в даних напрямках без суттєвого збiльшення робочих частот i ускладнення апаратної частини. Перевагою пропонованого методу є те, що програмна радiосистема може складатися з декiлькох ПЛIС i обслуговувати декiлька незалежних радiоканалiв, а перепрограмування властивостей дозволяє змiнювати число i складовi процесу обробки повiдомлень в залежностi вiд поточних умов роботи. Метод дослiдження. В роздiлi проаналiзовано паралельнiсть арифметичнi операцiї у системi залишкових класiв. Цi операцiї називаються модульними, оскiльки для обробки числових значень використовують невеликi залишки дiлення на певний набiр модулiв, а для додавання i множення потрiбно лише один тактовий цикл роботи обчислювальної системи. Для перетворення чисел iз двiйкової системи у RNS використовується алгоритм, заснований на застосуваннi китайської теореми про залишки. Проте такi операцiї, як подiл, порiвняння двох чисел i виявлення знака, є складними i ресурсо-затратними в RNS. Для цих проблемних операцiй було запропоновано кiлька рiшень. Вони полягають у вiдсутностi процесу перетвореннi залишку в бiнарну систему (зворотне перетворення) шляхом застосування цифро-аналогових перетворювачiв у RNS. З iншого боку, вибiр правильного набору модулiв є ще одним важливим питанням для побудови ефективного RNS з достатнiм динамiчним дiапазоном. Результати та аналiз. Пiдводячи пiдсумки деяких результатiв, можна зазначити, що система класiв залишкiв дозволяє значно полiпшити параметри обчислювача у SDR, а особливо у функцiональному блоковi Direct Digital Synthesizers (DDS) у порiвняннi з обчислювачем, побудованим на тiй же фiзичнiй i технологiчнiй основi, але в позицiйнiй обчислювальнiй системi, а також отримання нових бiльш прогресивних конструктивних i структурних рiшень. Експериментальнi результати показують, що представленi методи дають значнi переваги для цифрових фiльтрiв у SDR, якi характеризуються високим динамiчним дiапазоном i мають велику кiлькiстю ланок, особливо коли повнi перемножувачi не доступнi у цiльовiй архiтектурi FPGA, або коли цi перемножувачi повиннi використовуватися для рiзних цiлей. Висновки. Таким чином, запропонована система вносить явнi переваги перед iснуючими системами i показує переваги продуктивностi обчислювальних операцiй i може бути використана для побудови сучасних систем зв’язку. Запропонована архiтектура зменшує розмiри конвеєру суматорiв i перемножувачiв, що є дуже важливим фактором при розробцi високошвидкiсних SDR.Introduction. In the classic view, program-defined radio system (Software Defined Radio, SDR) is a central processor, equipped with receiving and transmitting units. In order to speed up computational operations in SDR systems it is proposed to use the system of residual classes as a mathematical basis. The results of research conducted by various groups of scientists in order to find ways to improve the performance of computing tools, methods of organizing an effective system for detecting and correcting errors, as well as building reliable computer systems, make it possible to assert that, within the limits of positional number systems, no fundamental changes can be expected in these areas without a significant increase in operating frequencies and hardware complications. The advantage of this method is that a software radio system can consist of several FPGAs and serve several independent radio channels, and reprogramming the properties allows you to change the number and components of message processors depending on current operating conditions. Research method. The equations in this section show the parallel nature of the RNS, free from bit transfers. These operations are called modular, because for it takes only one clock cycle to process the numerical values. To convert numbers from the binary position number system to RNS we use an algorithm based on the application of a distributed arithmetic. However, operations such as division, comparison of two numbers, and the detection of a sign are laborious and expensive in RNS Several decisions were proposed for these problem operations. They consist in the absence of the process of converting a residue into a binary system (reverse transformation) by using digital-to-analog converters in RNS. On the other hand, choosing the right set of modules is another important issue for building an effective RNS with a sufficient dynamic range. Results and analysis. Summing up some results, it can be noted that the system of residual classes allows to significantly improve the parameters of a computer in SDR especially in functional block a Direct Digital Synthesizers (DDS) in comparison with a computer built on the same physical and technological basis, but in a positional system calculation, and also to receive new more progressive constructive and structural solutions. The experimental results shows that the presented techniques offer interesting advantages for FIR filters characterized by high dynamic range and high number of taps especially when full custom multipliers are not available in the target FPGA architecture or when they must to be used for different purposes. Conclusion. Thus, the proposed system introduces clear advantages over existing systems and shows performance advantages and can be used to build modern communication systems. The proposed architecture reduces the size of the pipeline adders and multipliers which is a very important factor in the design SDR for fast work.В статье рассмотрены принципы построения и функционирования систем, определенных программным обеспечением (Software Defned Radio, SDR). С целью ускорения вычислительных операций в системах SDR предлагается применение системы остаточных классов в качестве математической основы построения систем. Преимуществом приведенного метода является то, что программная радиосистема может состоять из нескольких ПЛИС и обслуживать несколько независимых радиоканалов, а перепрограммирование свойств позволяет изменять число и составляющие процессоры сообщений в зависимости от текущих условий роботы. Приведены проблемы формирования выходного сигнала. Описаны особенности внедрения операций прямого и обратного преобразований с позиционных на непозиционые системы исчисления. Рассмотрена структурная модель SDR с прямыми цифровыми синтезаторами частоты, ЦАП, АЦП, цифровыми фильтрами в системе остаточных классов. Рассмотрены методы преобразования системы остаточных класов в аналоговый сигнал. Рассматриваются проблемы эффективного использования площади кристалла для SDR и уменьшения задержек в формировании выходного сигнала. Полученные результаты показывают широкие возможности применения программно определенной радиосистемы в системе остаточных классов

NASA Tech Briefs, June 2004

Topics covered include: COTS MEMS Flow-Measurement Probes; Measurement of an Evaporating Drop on a Reflective Substrate; Airplane Ice Detector Based on a Microwave Transmission Line; Microwave/Sonic Apparatus Measures Flow and Density in Pipe; Reducing Errors by Use of Redundancy in Gravity Measurements; Membrane-Based Water Evaporator for a Space Suit; Compact Microscope Imaging System with Intelligent Controls; Chirped-Superlattice, Blocked-Intersubband QWIP; Charge-Dissipative Electrical Cables; Deep-Sea Video Cameras Without Pressure Housings; RFID and Memory Devices Fabricated Integrally on Substrates; Analyzing Dynamics of Cooperating Spacecraft; Spacecraft Attitude Maneuver Planning Using Genetic Algorithms; Forensic Analysis of Compromised Computers; Document Concurrence System; Managing an Archive of Images; MPT Prediction of Aircraft-Engine Fan Noise; Improving Control of Two Motor Controllers; Electro-deionization Using Micro-separated Bipolar Membranes; Safer Electrolytes for Lithium-Ion Cells; Rotating Reverse-Osmosis for Water Purification; Making Precise Resonators for Mesoscale Vibratory Gyroscopes; Robotic End Effectors for Hard-Rock Climbing; Improved Nutation Damper for a Spin-Stabilized Spacecraft; Exhaust Nozzle for a Multitube Detonative Combustion Engine; Arc-Second Pointer for Balloon-Borne Astronomical Instrument; Compact, Automated Centrifugal Slide-Staining System; Two-Armed, Mobile, Sensate Research Robot; Compensating for Effects of Humidity on Electronic Noses; Brush/Fin Thermal Interfaces; Multispectral Scanner for Monitoring Plants; Coding for Communication Channels with Dead-Time Constraints; System for Better Spacing of Airplanes En Route; Algorithm for Training a Recurrent Multilayer Perceptron; Orbiter Interface Unit and Early Communication System; White-Light Nulling Interferometers for Detecting Planets; and Development of Methodology for Programming Autonomous Agents

Algorithm Based Fault Tolerance in Massively Parallel Systems

An A complex computer system consists of billions of transistors, miles of wires, and many interactions with an unpredictable environment. Correct results must be produced despite faults that dynamically occur in some of these components. Many techniques have been developed for fault tolerant computation. General purpose methods are independent of the application, yet incur an overhead cost which may be unacceptable for massively parallel systems. Algorithm-specific methods, which can operate at lower cost, are a developing alternative [1, 72]. This paper first reviews the general-purpose approach and then focuses on the algorithm-specific method, with an eye toward massively parallel processors. Algorithm-based fault tolerance has the attraction of low overhead; furthermore it addresses both the detection and also the correction problems. The principle is to build low-cost checking and correcting mechanism based exclusively on the redundancies inherent in the system