Discrimination of surface and volume states in fully depleted field-effect devices on thick insulator substrates

The behavior of electronic devices fabricated on thin, lightly doped semiconductor layers can be significantly influenced by very low levels of non-ideal charge states. Such devices typically operate in a fully depleted mode, and can exhibit significantly different electrical properties and characteristics than their bulk material counterparts. Traditional interpretation of device characteristics may identify the existence of such non-idealities, but fail to ascertain if the origin is from within the semiconductor layer or associated with the interfaces to adjacent dielectric materials. This leads to ambiguity in how to rectify the behavior and improve device performance. Characterizing non-idealities through electrical means requires adaptations in both measurement techniques and data interpretation. Some of these adaptations have been applied in material systems like silicon-on-insulator (SOI), however in systems where the semiconductor film becomes increasingly isolated on very thick insulators (i.e., glass), the device physics of operation presents new challenges. Overcoming the obstacles in interpretation can directly aid the technology development of thin semiconductor films on thick insulator substrates. The investigation is initiated by isolating the interface of crystalline silicon bonded to a thick boro-aluminosilicate glass insulator. The interface is studied through traditional bulk capacitance-voltage (C-V) methods, and the electrical fragility of the interface is exposed. This reveals the necessity to discriminate between interface states and bulk defect states. To study methods of discrimination, the physics of field-effect devices fabricated on isolated semiconducting films is explained. These devices operate in a fully depleted state; expressions that describe the C-V relationship with a single gate electrode are derived and explored. The discussion presents an explanation of how surface and volume charge states each contribute to the C-V characteristic behavior. Application of this adapted C-V theory is then applied to the gated-diode, a novel device which has proven to be instrumental in charge state discrimination. Through this adaptation, the gated-diode is used to extract recombination-generation parameters isolated to the top surface, bottom surface and within the volume of the film. The methodology is developed through an exploration of devices fabricated on SOI and silicon-on-glass (SiOG) substrates, and furthers the understanding needed to improve material quality and device performance

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts

Journal of Telecommunications and Information Technology, 2009, nr 4

kwartalni

Photodiodes and Image Sensors on Mechanically Flexible Ultra-Thin Silicon Chips-in-Foil

CMOS-Bildsensoren haben in den letzten zwei Jahrzehnten enorme technologische Fortschritte erfahren und sich als eine wettbewerbsfähige Alternative gegenüber CCDBildsensoren auf dem Markt etabliert. Reduziert man die Chipdicke von CMOSBildsensoren von normal 725 μm auf ≤ 30 μm, erhält man mechanisch flexible Bildaufnehmer. Gewölbte CMOS-Bildsensoren würden für die optische Wahrnehmung völlig neue Möglichkeiten eröffnen (wie z. B. bei Insektenaugen). Betrachtet man die auf dem Chip integrierten Bauelemente und Schaltungen unter mechanischen Spannungen, stellt man fest, dass ihre elektrischen und optoelektronischen Eigenschaften von der ausgeübten mechanischen Spannung beeinflusst werden. Für den technischen Einsatz ist eine vom mechanischen Zustand des Bildsensors unbeinflusste Funktion erforderlich. Der Einfluss von mechanischer Spannung auf die Bauelemente- und Schaltungs-Charakteristiken und seine Minimierung bzw. Kompensation sind daher von besonderem Interesse. In dieser Arbeit wurden die optischen und elektrischen Eigenschaften von passiven und aktiven Bauelementen, sowie integrierten Schaltungen auf monokristallinen gedünnten flexiblen Siliziumchips unter mechanischen Spannungen untersucht. Der Einfluss von mechanischen Spannungen auf optische Eigenschaften (spektrale Lichtempfindlichkeit, Dunkelstrom und elektronisches Rauschen) einzelner p-n-Übergang basierter Photodioden und Bildsensorarrays auf (100)-Siliziumwafern wurde theoretisch modelliert und experimentell charakterisiert. Weiterhin wurden die elektrischen Eigenschaften (Ladungsträgerbeweglichkeit, Schwellenspannung, 1/f Rauschen) von MOSFeldeffekttransistoren in Bezug auf mechanischen Spannungen charakterisiert und ihre Abhängigkeit von der Orientierung zur Kristallorientierung des Substrats untersucht. Integrierte Schaltungen, wie Bandgap-Referenzspannungsquellen, Operationsverstärker und SC-basierte Schaltungen wurden unter mechanischen Spannungen theoretisch betrachtet, entworfen, gefertigt und experimentell charakterisiert. Mit Hilfe des in dieser Arbeit vorgeschlagenen und eingesetzten Simulationskonzeptes, ist die Schaltungssimulation der obengenannten Abhängigkeiten möglich. Dadurch hat der Schaltungsentwickler die Möglichkeit Schaltungskonzepte zur Kompensation oder Minimierung der von der mechanischen Spannung hervorgerufenen Einflüsse zu simulieren. In dieser Hinsicht werden Schaltungskonzepte und Design-Regeln präsentiert, die den Einfluss von mechanischen Spannungen auf Bildsensorchips berücksichtigen und minimieren. Im Rahmen dieser Arbeit wurde darüber hinaus ein mechanisch flexibler Bildsensorchip entworfen, simuliert und gefertigt, dessen Betrieb unabhängig von der ausgeübten mechanischen Spannung ist. Der ultra-dünne 20 μm Bildsensorchip ist geeignet auf zylindrisch gewölbte Oberflächen aufgebracht zu werden und erlaubt die Aufnahme raumrichtungsselektiver optischer Informationen im Sinne eines Panoramablicks.CMOS image sensors (CIS) have experienced the last two decades tremendous technological advances rendering them a viable alternative to charged couple devices (CCDs) not only in high volume applications but also in applications which require high spatial and temporal resolution, high dynamic range, low noise or high sensitivity levels. CISs are employed due to their increased chip thickness (ca. 750 μm) solely in the traditional planar image acquisition. If the chip thickness could be reduced down to or less than 30 μm, the silicon chips would become mechanically flexible. Such flexible CISs could substantially extend the application spectrum of image sensors in non-conventional imaging systems (e.g. imitating insect vision). However, the on-chip integrated devices and circuits exhibit stress-induced changes on their electrical and optoelectronic characteristics. Since a stress independent operation is striven, the minimization or compensation of the influence of mechanical stress on the characteristics of devices and circuits is of great interest. In this work optical and electrical properties of passive and active devices as well as integrated circuits on ultra-thin monolithic flexible silicon chips have been investigated under the application of mechanical stress. The influence of mechanical stress on the optical characteristics (spectral sensitivity, dark current and electronic noise) of p-n junction based photodiodes and image sensor chips on (100)-silicon wafers have been theoretically modeled and experimentally characterized. Moreover, the electrical characteristics (carrier mobility, threshold voltage and 1/f noise) of mechanically strained MOS field-effect transistors and their dependence on the channel orientation on the substrate have been investigated. Integrated circuits such as bandgap reference voltage sources, operational amplifiers and switched capacitor (SC) based circuits have been theoretically treated, designed, fabricated and experimentally characterized. Within this framework a simulation technique has been proposed and deployed, which allows the simulation of the above mentioned stress dependence on device and circuit level. The analog circuit designer can employ the simulation technique toward the proposal of circuit topologies or techniques, which minimize or compensate the strain-induced changes on the circuit operation. In this direction, circuit concepts and design rules are proposed, which minimize the influence of mechanical stress on flexible CIS chips. Within the scope of this work, a mechanically flexible CMOS image sensor chip has been designed, simulated and fabricated, which operation is stress independent. The developed ultra-thin 20 μm CIS chip can be wrapped around a cylindrically curved surface and thus record panoramic optical information

Fabrication and characterization of germanium-on-silicon photodiodes

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 155-165).Germanium is becoming an increasingly popular material to use in photonic systems. Due to its strong absorption in the near infrared and its relative ease of integration on silicon, it is a promising candidate for the fabrication of CMOS-compatible photodetectors. The goal of this thesis is to understand the physics of Ge-on-Si photodiodes, especially the dark current. Low-pressure chemical vapor deposition was used to deposit thick (1 - 2 [mu]m) films on silicon substrates either selectively in oxide windows or in blanket films. Photodetectors were fabricated in both types of films and their optical and electronic properties are discussed. It was found that the main source of leakage current in these detectors is the generation of carriers at the Ge/passivation interface. This especially affects small devices, as the perimeter/area ratio is much larger than for large devices. A post-metallization anneal in nitrogen at 400°C was found to reduce the dark current of small devices (10 x 10 pm) by ~1000X at -1 V. The same anneal reduces the dark current of larger devices (100 x 100 [mu]m) by ~140X. Through metal-oxide-semiconductor capacitor and doping studies, it was found that the anneal draws holes to the surface of the germanium, leading to better isolation of the devices and reduced leakage current. It was also found that threading defects play a role in leakage current. Threading defects arise because of the 4% lattice mismatch between germanium and the underlying silicon. For 1 jim-thick germanium films, as-grown samples are expected to have -5 x 108 cm- 2 threading defects. At this level, these defects are the dominant leakage current mechanism. Annealing the films at high temperatures can reduce the defect density. Large-area (300 x 300 pm) devices fabricated with a post-metallization anneal and with a threading defect density of -2 x 107 cm-2 were found to have a dark current density of ~1 mA/cm2 and a responsivity of 0.32 A/W at -1 V and 1550 nm.by Nicole Ann DiLello.Ph.D

Caractérisation, mécanismes et applications mémoire des transistors avancés sur SOI

Ce travail présente les principaux résultats obtenus avec une large gamme de dispositifs SOI avancés, candidats très prometteurs pour les futurs générations de transistors MOSFETs. Leurs propriétés électriques ont été analysées par des mesures systématiques, agrémentées par des modèles analytiques et/ou des simulations numériques. Nous avons également proposé une utilisation originale de dispositifs FinFETs fabriqués sur ONO enterré en fonctionnalisant le ONO à des fins d'application mémoire non volatile, volatile et unifiées. Après une introduction sur l'état de l'art des dispositifs avancés en technologie SOI, le deuxième chapitre a été consacré à la caractérisation détaillée des propriétés de dispositifs SOI planaires ultra- mince (épaisseur en dessous de 7 nm) et multi-grille. Nous avons montré l excellent contrôle électrostatique par la grille dans les transistors très courts ainsi que des effets intéressants de transport et de couplage. Une approche similaire a été utilisée pour étudier et comparer des dispositifs FinFETs à double grille et triple grille. Nous avons démontré que la configuration FinFET double grille améliore le couplage avec la grille arrière, phénomène important pour des applications à tension de seuil multiple. Nous avons proposé des modèles originaux expliquant l'effet de couplage 3D et le comportement de la mobilité dans des TFTs nanocristallin ZnO. Nos résultats ont souligné les similitudes et les différences entre les transistors SOI et à base de ZnO. Des mesures à basse température et de nouvelles méthodes d'extraction ont permis d'établir que la mobilité dans le ZnO et la qualité de l'interface ZnO/SiO2 sont remarquables. Cet état de fait ouvre des perspectives intéressantes pour l'utilisation de ce type de matériaux aux applications innovantes de l'électronique flexible. Dans le troisième chapitre, nous nous sommes concentrés sur le comportement de la mobilité dans les dispositifs SOI planaires et FinFET en effectuant des mesures de magnétorésistance à basse température. Nous avons mis en évidence expérimentalement un comportement de mobilité inhabituel (multi-branche) obtenu lorsque deux ou plusieurs canaux coexistent et interagissent. Un autre résultat original concerne l existence et l interprétation de la magnétorésistance géométrique dans les FinFETs.L'utilisation de FinFETs fabriqués sur ONO enterré en tant que mémoire non volatile flash a été proposée dans le quatrième chapitre. Deux mécanismes d'injection de charge ont été étudiés systématiquement. En plus de la démonstration de la pertinence de ce type mémoire en termes de performances (rétention, marge de détection), nous avons mis en évidence un comportement inattendu : l amélioration de la marge de détection pour des dispositifs à canaux courts. Notre concept innovant de FinFlash sur ONO enterré présente plusieurs avantages: (i) opération double-bit et (ii) séparation de la grille de stockage et de l'interface de lecture augmentant la fiabilité et autorisant une miniaturisation plus poussée que des Finflash conventionnels avec grille ONO.Dans le dernier chapitre, nous avons exploré le concept de mémoire unifiée, en combinant les opérations non volatiles et 1T-DRAM par le biais des FinFETs sur ONO enterré. Comme escompté pour les mémoires dites unifiées, le courant transitoire en mode 1T-DRAM dépend des charges non volatiles stockées dans le ONO. D'autre part, nous avons montré que les charges piégées dans le nitrure ne sont pas perturbées par les opérations de programmation et lecture de la 1T-DRAM. Les performances de cette mémoire unifiée multi-bits sont prometteuses et pourront être considérablement améliorées par optimisation technologique de ce dispositif.The evolution of electronic systems and portable devices requires innovation in both circuit design and transistor architecture. During last fifty years, the main issue in MOS transistor has been the gate length scaling down. The reduction of power consumption together with the co-integration of different functions is a more recent avenue. In bulk-Si planar technology, device shrinking seems to arrive at the end due to the multiplication of parasitic effects. The relay has been taken by novel SOI-like device architectures. In this perspective, this manuscript presents the main achievements of our work obtained with a variety of advanced fully depleted SOI MOSFETs, which are very promising candidates for next generation MOSFETs. Their electrical properties have been analyzed by systematic measurements and clarified by analytical models and/or simulations. Ultimately, appropriate applications have been proposed based on their beneficial features.In the first chapter, we briefly addressed the short-channel effects and the diverse technologies to improve device performance. The second chapter was dedicated to the detailed characterization and interesting properties of SOI devices. We have demonstrated excellent gate control and high performance in ultra-thin FD SOI MOSFET. The SCEs are efficiently suppressed by decreasing the body thickness below 7 nm. We have investigated the transport and electrostatic properties as well as the coupling mechanisms. The strong impact of body thickness and temperature range has been outlined. A similar approach was used to investigate and compare vertical double-gate and triple-gate FinFETs. DG FinFETs show enhanced coupling to back-gate bias which is applicable and suitable for dynamic threshold voltage tuning. We have proposed original models explaining the 3D coupling effect in FinFETs and the mobility behavior in ZnO TFTs. Our results pointed on the similarities and differences in SOI and ZnO transistors. According to our low-temperature measurements and new promoted extraction methods, the mobility in ZnO and the quality of ZnO/SiO2 interface are respectable, enabling innovating applications in flexible, transparent and power electronics. In the third chapter, we focused on the mobility behavior in planar SOI and FinFET devices by performing low-temperature magnetoresistance measurements. Unusual mobility curve with multi-branch aspect were obtained when two or more channels coexist and interplay. Another original result in the existence of the geometrical magnetoresistance in triple-gate and even double-gate FinFETs.The operation of a flash memory in FinFETs with ONO buried layer was explored in the forth chapter. Two charge injection mechanisms were proposed and systematically investigated. We have discussed the role of device geometry and temperature. Our novel ONO FinFlash concept has several distinct advantages: double-bit operation, separation of storage medium and reading interface, reliability and scalability. In the final chapter, we explored the avenue of unified memory, by combining nonvolatile and 1T-DRAM operations in a single transistor. The key result is that the transient current, relevant for 1T-DRAM operation, depends on the nonvolatile charges stored in the nitride buried layer. On the other hand, the trapped charges are not disturbed by the 1T-DRAM operation. Our experimental data offers the proof-of-concept for such advanced memory. The performance of the unified/multi-bit memory is already decent but will greatly improve in the coming years by processing dedicated devices.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book