Safety Recommendations for Safety-Critical Design Patterns

The concept of design patterns, which is considered as one of the commonly used techniques in the development of software and hardware systems, is applicable to be used in the design of safety-critical embedded systems. While several safety metrics and assessment methods have been proposed to evaluate safety-critical systems, most of these methods cannot be used for safety-critical design patterns, due to the fact that a design pattern presents a high-level abstract solution to commonly recurring design problem and it is not related to a specific application or to a specific case. This paper proposes a system of safety recommendations for safety-critical design patterns, which can be used in the assessment of design patterns for safety-critical embedded systems to reflect the severity of failure in the target application. The proposed safety recommendations are based on the safety recommendations of the IEC 61508 standard, and contain additional 3 types of recommendations: weakly not recommend, weakly recommended, and moderately recommended

System-level linking of synthesised hardware and compiled software using a higher-order type system

Devices with tightly coupled CPUs and FPGA logic allow for the implementation of heterogeneous applications which combine multiple components written in hardware and software languages, including first-party source code and third-party IP. Flexibility in component relationships is important, so that the system designer can move components between software and hardware as the application design evolves. This paper presents a system-level type system and linker, which allows functions in software and hardware components to be directly linked at link time, without requiring any modification or recompilation of the components. The type system is designed to be language agnostic, and exhibits higher-order features, to enables design patterns such as notifications and callbacks to software from within hardware functions. We demonstrate the system through a number of case studies which link compiled software against synthesised hardware in the Xilinx Zynq platform

Roombots -- Mechanical Design of Self-Reconfiguring Modular Robots for Adaptive Furniture

We aim at merging technologies from information technology, roomware, and robotics in order to design adaptive and intelligent furniture. This paper presents design principles for our modular robots, called Roombots, as future building blocks for furniture that moves and self-reconfigures. The reconfiguration is done using dynamic connection and disconnection of modules and rotations of the degrees of freedom. We are furthermore interested in applying Roombots towards adaptive behaviour, such as online learning of locomotion patterns. To create coordinated and efficient gait patterns, we use a Central Pattern Generator (CPG) approach, which can easily be optimized by any gradient-free optimization algorithm. To provide a hardware framework we present the mechanical design of the Roombots modules and an active connection mechanism based on physical latches. Further we discuss the application of our Roombots modules as pieces of a homogenic or heterogenic mix of building blocks for static structures

May 9th, 2017

Reliability is a serious concern for future extreme-scale high-performance computing (HPC) systems. Projections based on the current generation of HPC systems and technology roadmaps suggest the prevalence of very high fault rates in future systems. While the HPC community has developed various resilience solutions, application-level techniques as well as system-based solutions, the solution space of HPC resilience techniques remains fragmented. There are no formal methods and metrics to investigate and evaluate resilience holistically in HPC systems that consider impact scope, handling coverage, and performance & power efficiency. Few of the current approaches are portable to newer architectures and software environments that will be deployed on future systems. In this talk, I will present a structured approach to the management of HPC resilience using the concept of resilience-based design patterns. A design pattern is a general repeatable solution to a commonly occurring problem. We identify the commonly occurring problems and solutions used to deal with faults, errors and failures in HPC systems. Each established solution is described in the form of a pattern that addresses concrete problems. We have developed a complete catalog of resilience design patterns, which provides designers with a collection of such reusable design elements. We have also defined a framework that enhances a designer's understanding of the important constraints and opportunities for the design patterns to be implemented and deployed at various layers of the system stack. This design framework may be used to establish mechanisms and interfaces to coordinate flexible fault management across hardware and software components. The framework also enables optimization of the cost-benefit trade-offs among performance, resilience, and power consumption. The overall goal of this work is to enable a systematic methodology for the design and evaluation of resilience technologies in extreme-scale HPC systems

Defensive ML: Defending Architectural Side-channels with Adversarial Obfuscation

Side-channel attacks that use machine learning (ML) for signal analysis have become prominent threats to computer security, as ML models easily find patterns in signals. To address this problem, this paper explores using Adversarial Machine Learning (AML) methods as a defense at the computer architecture layer to obfuscate side channels. We call this approach Defensive ML, and the generator to obfuscate signals, defender. Defensive ML is a workflow to design, implement, train, and deploy defenders for different environments. First, we design a defender architecture given the physical characteristics and hardware constraints of the side-channel. Next, we use our DefenderGAN structure to train the defender. Finally, we apply defensive ML to thwart two side-channel attacks: one based on memory contention and the other on application power. The former uses a hardware defender with ns-level response time that attains a high level of security with half the performance impact of a traditional scheme; the latter uses a software defender with ms-level response time that provides better security than a traditional scheme with only 70% of its power overhead.Comment: Preprint. Under revie

Single-pixel imaging 12 years on: a review

Modern cameras typically use an array of millions of detector pixels to capture images. By contrast, single-pixel cameras use a sequence of mask patterns to filter the scene along with the corresponding measurements of the transmitted intensity which is recorded using a single-pixel detector. This review considers the development of single-pixel cameras from the seminal work of Duarte et al. up to the present state of the art. We cover the variety of hardware configurations, design of mask patterns and the associated reconstruction algorithms, many of which relate to the field of compressed sensing and, more recently, machine learning. Overall, single-pixel cameras lend themselves to imaging at non-visible wavelengths and with precise timing or depth resolution. We discuss the suitability of single-pixel cameras for different application areas, including infrared imaging and 3D situation awareness for autonomous vehicles

Algorithm-circuit co-design for detecting symptomatic patterns in biological signals

The advancement in scaled Silicon technology has accelerated the development of a wide range of applications in various fields including medical technology. It has immensely contributed to finding solutions for monitoring general health as well as alleviating intractable disorders in the form of implantable and wearable systems. This necessitates the development of energy efficient and functionally efficacious systems. This thesis has explored the algorithm-circuit co-design approach for developing an energy efficient epileptic seizure detection processor which could be used for implantable epilepsy prosthesis. Novel wavelet transform based algorithms are proposed for accurate detection of epileptic seizures. Energy efficient techniques at circuit level such as power and clock gating are utilized along with error resiliency at algorithm level to implement these algorithms in TSMC $65$nm bulk-Si technology. Furthermore, the methodology is extended to develop a generic pattern detection system, which could be used for health monitoring. The wavelet transform along with mathematical metrics and Mel cepstrum are used to develop an algorithm which can detect generic patterns in biological audio signals. The application of algorithm-circuit co-design methodology helps in practically implementing this system into a low power design. Using approximation of coefficients and multiplier-less implementation, the Mel cepstrum algorithm is modified to optimize the hardware cost without losing its functional efficacy. The system is user-specific and scalable for detecting various patterns in biological signals. The methodologies mentioned in this thesis are intended towards development of user-scalable, energy efficient and highly efficacious systems for detection of patterns in variety of biological signals