Programmable rate modem utilizing digital signal processing techniques

The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery

Spectral Analysis Techniques using Prism Signal Processing

The Prism is a new signal processing module which implements fully recursive, linear phase FIR filtering, so its computational cost is fixed irrespective of filter length. The Prism also has negligible design cost. Recent work has demonstrated how, using simple design rules, a chain of six Prisms can create a narrowband filter with arbitrary central frequency and bandwidth. In this paper, the technique is applied to spectral analysis of data, whereby a sequence of filters is applied to a data set to provide narrow frequency analysis, yielding accurate estimates of the frequencies and amplitudes of spectral peaks in the data. Although this time domain technique remains computationally expensive compared to the FFT, it can identify and reject spectral leakage, offering an alternative analysis for low amplitude and/or adjacent spectral peaks, including hidden tones, where FFT discrimination may be limited

Sub-Mbps key-rate continuous-variable quantum key distribution with local-local-oscillator over 100 km fiber

We experimentally demonstrated a sub-Mbps key rate Gaussian-modulated coherent-state continuous-variable quantum key distribution (CV-QKD) over 100 km transmission distance. To efficiently control the excess noise, the quantum signal and the pilot tone are co-transmitted in fiber channel based on wide-band frequency and polarization multiplexing methods. Furthermore, a high-accuracy data-assisted time domain equalization algorithm is carefully designed to compensate the phase noise and polarization variation in low signal-to-noise ratio. The asymptotic secure key rate (SKR) of the demonstrated CV-QKD is experimentally evaluated to be 10.36 Mbps, 2.59 Mbps, and 0.69 Mbps over transmission distance of 50 km, 75 km, and 100 km, respectively. The experimental demonstrated CV-QKD system significantly improves transmission distance and SKR compared to the state-of-art GMCS CV-QKD experimental results, and shows the potential for long-distance and high-speed secure quantum key distribution.Comment: 4 pages, 7 figure

The design and implementation of a wideband digital radio receiver

Historically radio has been implemented using largely analogue circuitry. Improvements in mixed signal and digital signal processing technology are rapidly leading towards a largely digital approach, with down-conversion and filtering moving to the digital signal processing domain. Advantages of this technology include increased performance and functionality, as well as reduced cost. Wideband receivers place the heaviest demands on both mixed signal and digital signal processing technology, requiring high spurious free dynamic range (SFDR) and signal processing bandwidths. This dissertation investigates the extent to which current digital technology is able to meet these demands and compete with the proven architectures of analogue receivers. A scalable generalised digital radio receiver capable of operating in the HF and VHF bands was designed, implemented and tested, yielding instantaneous bandwidths in excess of 10 MHz with a spurious-free dynamic range exceeding 80 decibels below carrier (dBc). The results achieved reflect favourably on the digital receiver architecture. While the necessity for minimal analogue circuitry will possibly always exist, digital radio architectures are currently able to compete with analogue counterparts. The digital receiver is simple to manufacture, based on the use of largely commercial off-the-shelf (COTS) components, and exhibits extreme flexibility and high performance when compared with comparably priced analogue receivers

Non Co-Operative Detection of LPI/LPD Signals Via Cyclic Spectral Analysis

This research proposes and evaluates a novel technique for detecting LPI/LPD communication signals using a digital receiver primarily designed to detect radar signals, such as a Radar Warning Receiver (RWR) or an Electronic Support Measures (ESM) receiver. The proposed Cyclic Spectrum Analysis (CSA) receiver is a robust detector that takes advantage of the spectral correlation properties of second-order cyclostationary signals. A computationally efficient algorithm is used to estimate the Spectral Correlation Function (SCF). Using state-of-the-art FFT processing, it is expected that the proposed CSA receiver architecture could estimate the entire cyclic spectrum m approximately 0.6 ms. The estimate is then reduced to an energy related test statistic that is valid for all cycle frequencies within the receiver bandwidth. By producing an estimate of the cyclic spectrum, the CSA receiver also benefits post-detection tasks such as signal classification and exploitation. As modeled, the ideal CSA receiver detection performance is within 1.0 dB of the radiometer in benign signal environments and consistently outperforms the radiometer in adverse signal environments. The effect on detection performance when the CSA receiver is implemented with channelized and quadrature digital receiver architectures is also examined

Contribution to the design of continuous -time Sigma - Delta Modulators based on time delay elements

The research carried out in this thesis is focused in the development of a new class of data converters for digital radio. There are two main architectures for communication receivers which perform a digital demodulation. One of them is based on analog demodulation to the base band and digitization of the I/Q components. Another option is to digitize the band pass signal at the output of the IF stage using a bandpass Sigma-Delta modulator. Bandpass Sigma- Delta modulators can be implemented with discrete-time circuits, using switched capacitors or continuous-time circuits. The main innovation introduced in this work is the use of passive transmission lines in the loop filter of a bandpass continuous-time Sigma-Delta modulator instead of the conventional solution with gm-C or LC resonators. As long as transmission lines are used as replacement of a LC resonator in RF technology, it seems compelling that transmission lines could improve bandpass continuous-time Sigma-Delta modulators. The analysis of a Sigma- Delta modulator using distributed resonators has led to a completely new family of Sigma- Delta modulators which possess properties inherited both from continuous-time and discretetime Sigma-Delta modulators. In this thesis we present the basic theory and the practical design trade-offs of this new family of Sigma-Delta modulators. Three demonstration chips have been implemented to validate the theoretical developments. The first two are a proof of concept of the application of transmission lines to build lowpass and bandpass modulators. The third chip summarizes all the contributions of the thesis. It consists of a transmission line Sigma-Delta modulator which combines subsampling techniques, a mismatch insensitive circuitry and a quadrature architecture to implement the IF to digital stage of a receiver