Rationale for and design of a generic tiled hierarchical phased array beamforming architecture

The purpose of the phased array beamforming project is to develop a generic flexible efficient phased array receiver platform, using a mixed signal hardware/software-codesign approach. The results will be applicable to any radio (RF) system, but we will focus on satellite receiver (DVB-S) and radar applications. We will present a preliminary mapping of beamforming processing on a tiled architecture and determine its scalability.\ud \ud The functionality, size and cost constraints imply an integrated mixed signal CMOS solution. For a generic flexible multi-standard solution, a software defined radio approach is taken. Because a scalable and dependable solution is needed, a tiled hierarchical architecture is proposed with reconfigurable hardware to regain flexibility. A mapping is provided of beamforming on the proposed architecture. The advantages and disadvantages of each solution are discussed with respect to applicability and scalability.\ud \ud Different beamforming processing solutions can be mapped on the same proposed tiled hierarchical architecture. This provides a flexible, scalable and reconfigurable solution for a wide application domain. Beamforming is a data-driven streaming process which lends itself well for a regular scalable architecture. Beamsteering on the other hand is much more control-oriented and future work will focus on how to support beamsteering on the proposed architecture as well

REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS

New radar applications need to perform complex algorithms and process a large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low-power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression algorithms for real-time transceiver optimization is presented, and is based on a System-on-Chip architecture for reconfigurable hardware devices. This study also evaluates the performance of dedicated coprocessors as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion, which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through high-performance buses, to perform floating-point operations, control the processing blocks, and communicate with an external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band testbed together with a low-cost channel emulator for different types of waveforms

GSFC Annual Scan Technology Review SpaceCube On-Board Processor Update

No abstract availabl

Targeting Reconfigurable FPGA based SoCs using the MARTE UML profile: from high abstraction levels to code generation

International audienceAs SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools to handle SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical SoCs as they integrate adaptivity features to cope with mutable design requirements and environment needs. This paper presents a novel approach to address system adaptivity and reconfigurability. A generic model of reactive control is presented in a SoC codesign framework: Gaspard. Afterwards, control integration at different levels of the framework is illustrated for both functional specification and FPGA synthesis. The presented work is based on Model-Driven Engineering and the UML MARTE profile proposed by Object Management Group, for modeling and analysis of real-time embedded systems. The paper thus presents a complete design flow to move from high level MARTE models to code generation, for implementation of dynamically reconfigurable SoCs

Semantic programming model-based design

For a generic flexible efficient array antenna receiver platform a hierarchical tiled architecture has been proposed, giving a heterogeneous multi-processor system-on-chip (MPSoC), multiple chips on a board (MCoB) and multiple boards in a system (MBiS). A wide range of MPSoCs are predicted to be used in the near future but how to efficiently apply these designs remains an issue. We will advocate a model-based design approach and propose a single semantic (programming) model for representing the specification, design and implementation and allowing for verification, simulation, architecture definition and design space exploration.\ud \ud A single model for specification, (formal or functional) verification, simulation and programming an MPSoC has obvious as well as some less obvious advantages. It allows for model-based design down to the implementation, especially for hierarchical MPSoC architectures. Partitioning and mapping of the functionality to an architecture is commonly done manually. Using the proposed approach the feasibility of (partly) automated design space exploration is discussed for determining either a partitioning and mapping for a given architecture or an optimal architecture based on set constraints.\ud \ud The proposed hierarchical tiled architecture provides a flexible reconfigurable solution, however partitioning, mapping, modeling and programming such systems remains an issue. The proposed approach tackles these problems at a higher conceptual level, thereby exploiting the inherent composability and parallelism available in the formalism. Design space explorations is facilitated by allowing transformations between different partitionings and mappings. However, the generic applicability and limitations of this approach will need to be researched further.\ud \u

Towards effective modeling and programming multi-core tiled reconfigurable architectures

For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigurable solution, but partitioning, mapping, modeling and programming such systems remains an issue. We will advocate a model-based design approach and propose a single semantic (programming) model for representing the specification, design and implementation. This approach tackles these problems at a higher conceptual level, thereby exploiting the inherent composability and parallelism available in the formalism. A case study illustrates the use of the semantic model with examples from analogue/digital co-design and hardware/software co-design

Adapting the SpaceCube v2.0 Data Processing System for Mission-Unique Application Requirements

The SpaceCube (sup TM) v2.0 system is a superior high performance, reconfigurable, hybrid data processing system that can be used in a multitude of applications including those that require a radiation hardened and reliable solution. This paper provides an overview of the design architecture, flexibility, and the advantages of the modular SpaceCube v2.0 high performance data processing system for space applications. The current state of the proven SpaceCube technology is based on nine years of engineering and operations. Five systems have been successfully operated in space starting in 2008 with four more to be delivered for launch vehicle integration in 2015. The SpaceCube v2.0 system is also baselined as the avionics solution for five additional flight projects and is always a top consideration as the core avionics for new instruments or spacecraft control. This paper will highlight how this multipurpose system is currently being used to solve design challenges of three independent applications. The SpaceCube hardware adapts to new system requirements by allowing for application-unique interface cards that are utilized by reconfiguring the underlying programmable elements on the core processor card. We will show how this system is being used to improve on a heritage NASA GPS technology, enable a cutting-edge LiDAR instrument, and serve as a typical command and data handling (C&DH) computer for a space robotics technology demonstration

The development of a node for a hardware reconfigurable parallel processor

This dissertation concerns the design and implementation of a node for a hardware reconfigurable parallel processor. The hardware that was developed allows for the further development of a parallel processor with configurable hardware acceleration. Each node in the system has a standard microprocessor and reconfigurable logic device and has high speed communications channels for inter-node communication. The design of the node provided high-speed serial communications channels allowing the implementation of various network topographies. The node also provided a PCI master interface to provide an external interface and communicate with local nodes on the bus. A high speed RlSC processor provided communication and system control functions and the reconfigurable logic device provided communication interfaces and data processing functions. The node was designed and implemented as a PCI card that interfaced a standard PCI bus. VHDL designs for logic devices that provided system support were developed, VHDL designs for the reconfigurable logic FPGA and software including drivers and system software were written for the node. The 64-bit version Linux operating system was then ported to the processor providing a UNIX environment for the system. The node functioned as specified and parallel and hardware accelerated processing was demonstrated. The hardware acceleration was shown to provide substantial performance benefits for the system