Energy-Efficient Time-Based Encoders and Digital Signal Processors in Continuous Time

Continuous-time (CT) data conversion and continuous-time digital signal processing (DSP) are an interesting alternative to conventional methods of signal conversion and processing. This alternative proposes time-based encoding that may not suffer from aliasing; shows superior spectral properties (e.g. no quantization noise floor); and enables time-based, event-driven, flexible signal processing using digital circuits, thus scaling well with technology. Despite these interesting features, this approach has so far been limited by the CT encoder, due to both its relatively poor energy efficiency and the constraints it imposes on the subsequent CT DSP. In this thesis, we present three principles that address these limitations and help improve the CT ADC/DSP system. First, an adaptive-resolution encoding scheme that achieves first-order reconstruction with simple circuitry is proposed. It is shown that for certain signals, the scheme can significantly reduce the number of samples generated per unit of time for a given accuracy compared to schemes based on zero-order-hold reconstruction, thus promising to lead to low dynamic power dissipation at the system level. Presented next is a novel time-based CT ADC architecture, and associated encoding scheme, that allows a compact, energy-efficient circuit implementation, and achieves first-order quantization error spectral shaping. The design of a test chip, implemented in a 0.65-V 28-nm FDSOI process, that includes this CT ADC and a 10-tap programmable FIR CT DSP to process its output is described. The system achieves 32 dB – 42 dB SNDR over a 10 MHz – 50 MHz bandwidth, occupies 0.093 mm2, and dissipates 15 µW–163 µW as the input amplitude goes from zero to full scale. Finally, an investigation into the possibility of CT encoding using voltage-controlled oscillators is undertaken, and it leads to a CT ADC/DSP system architecture composed primarily of asynchronous digital delays. The latter makes the system highly digital and technology-scaling-friendly and, hence, is particularly attractive from the point of view of technology migration. The design of a test chip, where this delay-based CT ADC/DSP system architecture is used to implement a 16-tap programmable FIR filter, in a 1.2-V 28-nm FDSOI process, is described. Simulations show that the system will achieve a 33 dB – 40 dB SNDR over a 600 MHz bandwidth, while dissipating 4 mW

Bezprzewodowa Jednostka Audio

Mestrado em Engenharia ElectrónicaA presente tese pretende descrever o desenvolvimento de um sistema electrónico, cuja funcionalidade se baseia na transmissão de sinais áudio através da rede Wireless. Inicialmente foi estudada a família de microcontroladores PIC32, no qual se incluiu a sua forma de programação. Foi ainda realizada pesquisa acerca dos possíveis métodos de compressão de áudio, culminando com o desenvolvimento de algoritmos de compressão no software MATLAB. Seguidamente foi desenvolvida a PIC32 Module – daughterboard do projecto. Esta é uma componente universal que contém um microcontrolador PIC32, de fácil utilização em outros projectos. Posteriormente foi criado o dispositivo Wireless Audio Unit – o objectivo basilar desta tese. Este passo compreendeu a esquematização e PCB de ambas as partes: o transmissor e o receptor. Após a montagem, ambos os dispositivos forma colocados em caixas. O firmware dos dois microcontroladores PIC32 foi criado em linguagem de programação C. O ADC e o DAC são controlados pelo firmware do PIC32, estando a ser executadas correctamente as suas funções. No momento do desenvolvimento da componente escrita desta tese, ainda se mantêm alguns problemas associados à manipulação do transceptor. Por esta razão, o firmware WAU não foi terminado, e o dispositivo não cumpre, ainda, a sua funcionalidade.The thesis aims to report on the development of an electronic system, which task is to transmit wirelessly an audio signal. The work was started by studying the PIC32 family of microcontrollers including the way of programming. The research on audio compression methods that was made, finished with development of compression algorithms in MATLAB software. Following, the PIC32 Module – the daughterboard of project was designed. This part is universal unit containing PIC32 microcontroller, which could be easily used in many other projects. Afterwards, it was created the proper Wireless Audio Unit device – the main objective of this dissertation. This step included design of schematics and PCB for two its parts: transmitter and receiver. After assembling, both devices was put into enclosures. The firmware for two PIC32 microcontrollers was created in C programming language. The ADC and DAC are controlled by PIC32 firmware and are correctly realizing their functions. At the moment of writing this document, the problem with handling transceiver was not solved. For this reason the firmware WAU was not finished and the device does not have its functionality.Celem niniejszego dokumentu jest opis wykonanego systemu elektronicznego, którego zadaniem jest bezprzewodowa transmisja sygnału audio. Praca została rozpoczęta od zapoznania się z rodziną mikrokontrolerów PIC32, włączając w to poznanie metod ich programowania. Badania nad istniejącymi metodami kompresji audio, zostały uwieńczone opracowaniem algorytmów kompresji w oprogramowaniu MATLAB. Następnie został zaprojektowany moduł rozszerzenia - PIC32 Module. Jest to uniwersalna jednostka zawierająca mikrokontroler PIC32, która może być łatwo wykorzystana również w innych projektach. Kolejnym krokiem było stworzenie właściwego urządzenia – Wireless Audio Unit (Bezprzewodowa Jednostka Audio), będącego głównym celem tej pracy. Etap ten zawierał projekt schematu oraz płytki obwodu drukowanego dwóch części projektu: WAU Transmitter (Nadajnik) i WAU Receiver (odbiornik). Po montażu, oba urządzenia zostały umieszczone w obudowach. Oprogramowanie dla mikrokontrolerów PIC32 zostało stworzone w języku programowania C. Przetworniki a/c oraz c/a są kontrolowane przez mikrokontroler i poprawnie realizują swoje funkcje. W chwili powstawania tego raportu, problem z obsługą transceivera nie został rozwiązany. Z tego powodu, oprogramowanie dla mikrokontrolerów nie zostało ukończone i urządzenie nie posiada założonej funkcjonalności

Design and VLSI implementation of a decimation filter for hearing Aid applications

Approximately 10% of the world’s population suffers from some type of hearing loss, yet only small percentage of this statistic use the hearing aid. The stigma associated with wearing a hearing aid, customer dissatisfaction with hearing aid performance, the cost and the battery life. Through the use of digital signal processing the digital hearing aid now offers what the analog hearing aid cannot offer. Currently lot of attention is being given to low power VLSI design. More and more people around the world suffer from hearing losses. The increasing average age and the growing population are the main reasons for this. The decimation filter used for hearing aid applications is designed and implemented both in MATLAB and VHDL. The decimation filter is designed using the distributed arithmetic multiplier in VHDL. Each digital filter structure is simulated using Matlab and its complete architecture is captured using Simulink. The resulting architecture is hardware efficient and consumes less power compared to conventional decimation filters. Compared to the comb-FIR-FIR architecture, the designed decimation filter architecture using Comb-half band FIR-FIR contributes to a hardware saving and reduces the power dissipation

Survey of error concealment schemes for real-time audio transmission systems

This thesis presents an overview of the main strategies employed for error detection and error concealment in different real-time transmission systems for digital audio. The “Adaptive Differential Pulse-Code Modulation (ADPCM)”, the “Audio Processing Technology Apt-x100”, the “Extended Adaptive Multi-Rate Wideband (AMR-WB+)”, the “Advanced Audio Coding (AAC)”, the “MPEG-1 Audio Layer II (MP2)”, the “MPEG-1 Audio Layer III (MP3)” and finally the “Adaptive Transform Coder 3 (AC3)” are considered. As an example of error management, a simulation of the AMR-WB+ codec is included. The simulation allows an evaluation of the mechanisms included in the codec definition and enables also an evaluation of the different bit error sensitivities of the encoded audio payload.Ingeniería Técnica en Telemátic