276 research outputs found

    Architectures and Algorithms for the Signal Processing of Advanced MIMO Radar Systems

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    This thesis focuses on the research, development and implementation of novel concepts, architectures, demonstrator systems and algorithms for the signal processing of advanced Multiple Input Multiple Output (MIMO) radar systems. The key concept is to address compact system, which have high resolutions and are able to perform a fast radar signal processing, three-dimensional (3D), and four-dimensional (4D) beamforming for radar image generation and target estimation. The idea is to obtain a complete sensing of range, Azimuth and elevation (additionally Doppler as the fourth dimension) from the targets in the radar captures. The radar technology investigated, aims at addressing sev- eral civil and military applications, such as surveillance and detection of targets, both air and ground based, and situational awareness, both in cars and in flying platforms, from helicopters, to Unmanned Aerial Vehicles (UAV) and air-taxis. Several major topics have been targeted. The development of complete systems and innovative FPGA, ARM and software based digital architectures for 3D imaging MIMO radars, which operate in both Time Division Multiplexing (TDM) and Frequency Divi- sion Multiplexing (FDM) modes, with Frequency Modulated Continuous Wave (FMCW) and Orthogonal Frequency Division Multiplexing (OFDM) signals, respectively. The de- velopment of real-time radar signal processing, beamforming and Direction-Of-Arrival (DOA) algorithms for target detection, with particular focus on FFT based, hardware implementable techniques. The study and implementation of advanced system concepts, parametrisation and simulation of next generation real-time digital radars (e.g. OFDM based). The design and development of novel constant envelope orthogonal waveforms for real-time 3D OFDM MIMO radar systems. The MIMO architectures presented in this thesis are a collection of system concepts, de- sign and simulations, as well as complete radar demonstrators systems, with indoor and outdoor measurements. Several of the results shown, come in the form of radar images which have been captured in field-test, in different scenarios, which aid in showing the proper functionality of the systems. The research activities for this thesis, have been carried out on the premises of Air- bus, based in Munich (Germany), as part of a Ph.D. candidate joint program between Airbus and the Polytechnic Department of Engineering and Architecture (Dipartimento Politecnico di Ingegneria e Architettura), of the University of Udine, based in Udine (Italy).Questa tesi si concentra sulla ricerca, lo sviluppo e l\u2019implementazione di nuovi concetti, architetture, sistemi dimostrativi e algoritmi per l\u2019elaborazione dei segnali in sistemi radar avanzati, basati su tecnologia Multiple Input Multiple Output (MIMO). Il con- cetto chiave `e quello di ottenere sistemi compatti, dalle elevate risoluzioni e in grado di eseguire un\u2019elaborazione del segnale radar veloce, un beam-forming tri-dimensionale (3D) e quadri-dimensionale (4D) per la generazione di immagini radar e la stima delle informazioni dei bersagli, detti target. L\u2019idea `e di ottenere una stima completa, che includa la distanza, l\u2019Azimuth e l\u2019elevazione (addizionalmente Doppler come quarta di- mensione) dai target nelle acquisizioni radar. La tecnologia radar indagata ha lo scopo di affrontare diverse applicazioni civili e militari, come la sorveglianza e la rilevazione di targets, sia a livello aereo che a terra, e la consapevolezza situazionale, sia nelle auto che nelle piattaforme di volo, dagli elicotteri, ai Unmanned Aerial Vehicels (UAV) e taxi volanti (air-taxis). Le tematiche affrontante sono molte. Lo sviluppo di sistemi completi e di architetture digitali innovative, basate su tecnologia FPGA, ARM e software, per radar 3D MIMO, che operano in modalit`a Multiplexing Time Division Multiplexing (TDM) e Multiplexing Frequency Diversion (FDM), con segnali di tipo FMCW (Frequency Modulated Contin- uous Wave) e Orthogonal Frequency Division Multiplexing (OFDM), rispettivamente. Lo sviluppo di tecniche di elaborazione del segnale radar in tempo reale, algoritmi di beam-forming e di stima della direzione di arrivo, Direction-Of-Arrival (DOA), dei seg- nali radar, per il rilevamento dei target, con particolare attenzione a processi basati su trasformate di Fourier (FFT). Lo studio e l\u2019implementazione di concetti di sistema avan- zati, parametrizzazione e simulazione di radar digitali di prossima generazione, capaci di operare in tempo reale (ad esempio basati su architetture OFDM). Progettazione e sviluppo di nuove forme d\u2019onda ortogonali ad inviluppo costante per sistemi radar 3D di tipo OFDM MIMO, operanti in tempo reale. Le attivit`a di ricerca di questa tesi sono state svolte presso la compagnia Airbus, con sede a Monaco di Baviera (Germania), nell\u2019ambito di un programma di dottorato, svoltosi in maniera congiunta tra Airbus ed il Dipartimento Politecnico di Ingegneria e Architettura dell\u2019Universit`a di Udine, con sede a Udine

    Advanced Three-Phase Grid Synchronization Using Synchronous Reference Frame Phase-Locked Loops

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    Modern power electronics devices require grid synchronization to accurately time the switching of their semiconductor devices. This project steps through the development of such an algorithm for three-phase grids. The classical synchronous reference frame phase-locked loop is studied in depth, including a detailed analysis of the transforms that give rise to its name. A few improvements are added in order to mitigate some of the well-known pitfalls of this method. Using the theory of symmetrical sequence components, new equations that describe the behaviour of said components in relation to unbalanced three-phase voltages are derived. These equations are then used to better understand the behaviour of the classical algorithm under unbalanced conditions. From this, an advanced grid synchronization algorithm based on multiple phase-locked loops is developed. This algorithm is then discretized and implemented in a typical microcontroller. Finally, a custom genetic algorithm is used to fine-tune the parameters of the algorithm to a specific simulated scenario meant to represent harsh grid conditions

    The Miniaturization of the AFIT Random Noise Radar

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    Advances in technology and signal processing techniques have opened the door to using an UWB random noise waveform for radar imaging. This unique, low probability of intercept waveform has piqued the interest of the U.S. DoD as well as law enforcement and intelligence agencies alike. While AFIT\u27s noise radar has made significant progress, the current architecture needs to be redesigned to meet the space constraints and power limitations of an aerial platform. This research effort is AFIT\u27s first attempt at RNR miniaturization and centers on two primary objectives: 1) identifying a signal processor that is compact, energy efficient, and capable of performing the demanding signal processing routines and 2) developing a high-speed correlation algorithm that is suited for the target hardware. A correlation routine was chosen as the design goal because of its importance to the noise radar\u27s ability to estimate the presence of a return signal. Furthermore, it is a computationally intensive process that was used to determine the feasibility of the processing component. To determine the performance of the proposed algorithm, results from simulation and experiments involving representative hardware were compared to the current system. Post-implementation reports of the FPGA-based correlator indicated zero timing failures, less than a Watt of power consumption, and a 44% utilization of the Virtex-5\u27s logic resources

    Development of real-time cellular impedance analysis system

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    The cell impedance analysis technique is a label-free, non-invasive method, which simplifies sample preparation and allows applications requiring unmodified cell retrieval. However, traditional impedance measurement methods suffer from various problems (speed, bandwidth, accuracy) for extracting the cellular impedance information. This thesis proposes an improved system for extracting precise cellular impedance in real-time, with a wide bandwidth and satisfactory accuracy. The system hardware consists of five main parts: a microelectrode array (MEA), a stimulation circuit, a sensing circuit, a multi-function card and a computer. The development of system hardware is explored. Accordingly, a novel bioimpedance measurement method coined digital auto balancing bridge method, which is improved from the traditional analogue auto balancing bridge circuitry, is realized for real-time cellular impedance measurement. Two different digital bridge balancing algorithms are proposed and realized, which are based on least mean squares (LMS) algorithm and fast block LMS (FBLMS) algorithm for single- and multi-frequency measurements respectively. Details on their implementation in FPGA are discussed. The test results prove that the LMS-based algorithm is suitable for accelerating the measurement speed in single-frequency situation, whilst the FBLMS-based algorithm has advantages in stable convergence in multi-frequency applications. A novel algorithm, called the All Phase Fast Fourier Transform (APFFT), is applied for post-processing of bioimpedance measurement results. Compared with the classical FFT algorithm, the APFFT significantly reduces spectral leakage caused by truncation error. Compared to the traditional FFT and Digital Quadrature Demodulation (DQD) methods, the APFFT shows excellent performance for extracting accurate phase and amplitude in the frequency spectrum. Additionally, testing and evaluation of the realized system has been performed. The results show that our system achieved a satisfactory accuracy within a wide bandwidth, a fast measurement speed and a good repeatability. Furthermore, our system is compared with a commercial impedance analyzer (Agilent 4294A) in biological experiments. The results reveal that our system achieved a comparable accuracy to the commercial instrument in the biological experiments. Finally, conclusions are given and the future work is proposed

    Engineering Trade-off Considerations Regarding Design-for-Security, Design-for-Verification, and Design-for-Test

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    The United States government has identified that application specific integrated circuit (ASIC) and field programmable gate array (FPGA) hardware are at risk from a variety of adversary attacks. This finding affects system security and trust. Consequently, processes are being developed for system mitigation and countermeasure application. The scope of this tutorial pertains to potential vulnerabilities and countermeasures within the ASIC/FPGA design cycle. The presentation demonstrates how design practices can affect the risk for the adversary to: change circuitry, steal intellectual property, and listen to data operations. An important portion of the design cycle is assuring the design is working as specified or as expected. This is accomplished by exhaustive testing of the target design. Alternatively, it has been shown that well established schemes for test coverage enhancement (design-for-verification (DFV) and design-for-test (DFT)) can create conduits for adversary accessibility. As a result, it is essential to perform a trade between robust test coverage versus reliable design implementation. The goal of this tutorial is to explain the evolution of design practices; review adversary accessibility points due to DFV and DFT circuitry insertion (back door circuitry); and to describe common engineering trade-off considerations for test versus adversary threats
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