MEMS Technologies for Energy Harvesting

The objective of this chapter is to introduce the technology of Microelectromechanical Systems, MEMS, and their application to emerging energy harvesting devices. The chapter begins with a general introduction to the most common MEMS fabrication processes. This is followed with a survey of design mechanisms implemented in MEMS energy harvesters to provide nonlinear mechanical actuations. Mechanisms to produce bistable potential will be studied, such as introducing fixed magnets, buckling of beams or using slightly slanted clamped-clamped beams. Other nonlinear mechanisms are studied such as impact energy transfer, or the design of nonlinear springs. Finally, due to their importance in the field of MEMS and their application to energy harvesters, an introduction to actuation using piezoelectric materials is given. Examples of energy harvesters found in the literature using this actuation principle are also presented

Above-IC RF MEMS devices for communication applications

Wireless communications are showing an explosive growth in emerging consumer and military applications of radiofrequency (RF), microwave, and millimeter-wave circuits and systems. Applications include wireless personal connectivity (Bluetooth), wireless local area networks (WLAN), mobile communication systems (GSM, GPRS, UMTS, CDMA), satellite communications and automotive electronics. Future cell phones and ground communication systems as well as communication satellites will require more and more sophisticated technologies. The increasing demand for size and weight reduction, cost savings, low power consumption, increased frequency and higher functionality and reconfigurability as part of multiband and multistandard operation is necessitating the use of highly integrated RF front-end circuits. Chip scaling has made a major contribution to this goal, but today a situation has been reached where the presence of numerous off-chip passive RF components imposes a critical bottleneck to further integration and miniaturization of wireless transceivers. Microelectromechanical systems (MEMS) technology is a rapidly emerging enabling technology that is intended to replace the discrete passives by their integrated counterparts. In this thesis, an original metal surface micromachining process, which is compatible with CMOS post-processing, for above-IC integration of RF MEMS tunable capacitors and suspended inductors is presented. A detailed study on SF6 inductively coupled plasma (ICP) releasing has been performed in order to ascertain the optimal process parameters. This study has emphasized the fact that temperature plays an important role in this process by limiting silicon dioxide etching. Moreover, the optimized recipe has been found to be independent of the sacrificial layer used (amorphous or polycrystalline silicon) and its thickness. Using this recipe, 15.6 µm/min Si underetch rate with high Si: SiO2 selectivity (> 20000: 1) has been obtained. Single-air-gap and double-air-gap parallel-plate MEMS tunable capacitors have been designed, fabricated and characterized in the pF range, from 1 MHz to 13.5 GHz. It has been shown that an optimized design of the suspended membrane and direct symmetrical current feed at both ports can significantly improve the quality factor and increase the self-resonant frequency, pushing it to 12 GHz and beyond. The maximum capacitance tuning range obtained for a single-air-gap capacitor is 29% for a bias voltage of 20 V. The maximum capacitance tuning range obtained for a double-air-gap capacitor is 207% for a bias voltage of 70 V. The post-processing of X-FAB BiCMOS wafers has been successfully demonstrated to fabricate monolithically integrated VCOs with above-IC MEMS LC tank. Comparing a suspended inductor and the X-FAB inductor with the same design, it has been shown that increasing the thickness of the spiral from 2.3 to 4 µm and having the spiral suspended 3 µm above the passivation layers lead to an improvement factor of 2 for the peak quality factor and a shift of the self-resonant frequency beyond 15 GHz. No significant variation on bipolar and MOS transistors characteristics due to the post-processing has been observed and we conclude that the variation due to post-processing is in the same range as the wafer-to-wafer variation. Based on our metal surface micromachining process, coplanar waveguide (CPW) MEMS shunt capacitive switches and variable true-time delay lines (V-TTDLs) have been designed, fabricated and characterized in the 1 - 20 GHz range. A novel MEMS device architecture: the SG-MOSFET, which combines a solid-state MOS transistor and a metal suspended gate has been proposed as DC current switch. The corresponding fabrication process using polysilicon as a sacrificial layer has been developed to release metal gate suspended over gate oxide by SF6 plasma. Very abrupt current switches have been demonstrated with subthreshold slope better than 10 mV/decade (better than the theoretical solid-state bulk or SOI MOSFET limit of 60 mV/decade) and ultra-low gate leakage (less than 0.001 pA/µm2) due to the air-gap

Fabrication of high aspect ratio vibrating cylinder microgyroscope structures by use of the LIGA process

Inertial grade microgyroscopes are of great importance to improve and augment inertial navigation systems based on GPS for industrial, automotive, and military applications. The efforts by various research groups worldwide to develop inertial grade microgyroscopes have not been successful to date. In 1994, the Department of Mechanical Engineering at Louisiana State University and SatCon Technology Corporation (Boston, Massachusetts) proposed a series of shock tolerant micromachined vibrating cylinder rate gyroscopes with aspect ratios of up to 250:1 to meet the needs of inertial navigation systems based on existing conventional vibrating cylinder gyroscopes. Each microgyroscope consisted of a tall thin shell metallic cylinder attached to a substrate at one end and surrounded by four drive- and four sense-electrodes. The proposed drive- and sense-mechanisms were capacitive-force and capacitance-change, respectively. Since the high aspect ratio metallic microgyroscope structures could not be fabricated by using traditional silicon-based MEMS processes, a LIGA-based two layer fabrication process was developed. A wiring layer was constructed by using a combination of thick film photolithography and electroplating (nickel and gold) on a silicon substrate covered with silicon nitride and a tri-layer plating base; aligned X-ray lithography and nickel electroplating were used to build the high aspect ratio cylinders and electrodes. Deficiencies in the LIGA process were also addressed in this research. Three types of X-ray mask fabrication processes for multi-level LIGA were developed on graphite, borosilicate glass and silicon nitride substrates. Stable and reliable gold electroplating methods for X-ray masks were also established. The plating rate and internal stress of deposits were thoroughly characterized for two brands of commercially available sulfite-based gold electroplating solutions, Techni Gold 25E and NEUTRONEX 309. The gaps between the cylinders and electrodes, which are defined by thin PMMA walls during electroplating, were found to be smaller than designed and deformed in many of the microgyroscope structures. The lateral dimensional loss (LDL) and deformation were identified to be related to the overall thickness and lateral aspect ratio (LAR) of the thin PMMA walls

Single- and dual-axis lateral capacitive accelerometers based on CMOS-MEMS technology

In order to have a compatible device in a sensor node in wireless sensor network, the sensors have to be made in micro-size, low cost, low power consumption and high performance. By using CMOS-MEMS technology, the micro sensors can be implemented with promising results. One of the central micro inertial sensors is an accelerometer which has the capability of sensing position change, vibration and shock of a device. A single-axis lateral capacitive accelerometer and a dual-axis in-plane capacitive accelerometer are made in this thesis. An alternative design of the single-axis accelerometer is discussed. The system designs are made through mathematical analysis in MatLab, 3D FEM simulation in CoventorWare and final layout in Cadence. The main issue is making compliant springs, large proof mass, considerable number of comb fingers, for fabricating micro sensors with high sensitivity and good noise performance. The single-axis lateral capacitive accelerometer has sensor sensitivity of 9.3mV/G, mechanical noise floor of 19uG/squareroot(Hz), linear measuring range of ±26G. The dual-axis in-plane capacitive accelerometer has sensor sensitivity of 9.3mV/G in one direction and 11.1mV/G in the cross direction. The chip is fabricated in a 0.25um BiCMOS process from STMicroelectronics. The post process is done at Carnegie Mellon University (CMU), USA and SINTEF MiNaLab, Norway

Development and Packaging of Microsystems Using Foundry Services

Micro-electro-mechanical systems (MEMS) are a new and rapidly growing field of research. Several advances to the MEMS state of the art were achieved through design and characterization of novel devices. Empirical and theoretical model of polysilicon thermal actuators were developed to understand their behavior. The most extensive investigation of the Multi-User MEMS Processes (MUMPs) polysilicon resistivity was also performed. The first published value for the thermal coefficient of resistivity (TCR) of the MUMPs Poly 1 layer was determined as 1.25 x 10(exp -3)/K. The sheet resistance of the MUMPs polysilicon layers was found to be dependent on linewidth due to presence or absence of lateral phosphorus diffusion. The functional integration of MEMS with CMOS was demonstrated through the design of automated positioning and assembly systems, and a new power averaging scheme was devised. Packaging of MEMS using foundry multichip modules (MCMs) was shown to be a feasible approach to physical integration of MEMS with microelectronics. MEMS test die were packaged using Micro Module Systems MCM-D and General Electric High Density Intercounect and Chip-on-Flex MCM foundries. Xenon difluoride (XeF2) was found to be an excellent post-packaging etchant for bulk micromachined MEMS. For surface micromachining, hydrofluoric acid (HF) can be used

Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

The emerging three-dimensional (3D) integration technology is expected to lead to an industry paradigm shift due to its tremendous benefits. Intense research activities are going on about technology, simulation, design, and product prototypes. This thesis work aims at fabricating through-silicon vias (TSVs) on diced processor chips, and later bonding them into a 3D-stacked chip. How to handle and process delicate processor chips with high alignment precision is a key issue. The TSV process to be developed also needs to adapt to this constraint. Four TSV processes have been studied. Among them, the ring-trench TSV process demonstrates the feasibility of fabricating TSVs with the prevailing dimensions, and the whole-through TSV process achieves the first dummy chip post-processed with TSVs in EPFL although the dimension is rather large to keep a reasonable aspect ratio (AR). Four self-alignment (SA) techniques have been investigated, among which the gravitational SA and the hydrophobic SA are found to be quite promising. Using gravitational SA, we come to the conclusion that cavities in silicon carrier wafer with a profile angle of 60° can align the chips with less than 20 µm inaccuracies. The alignment precision can be improved after adopting more advanced dicing tools instead of using the traditional dicing saws and larger cavity profile angle. Such inaccuracy will be sufficient to align the relatively large TSVs for general products such as 3D image sensors. By fabricating bottom TSVs in the carrier wafer, a 3D silicon interposer idea has been proposed to stack another chip, e.g. a processor chip, on the other side of the carrier wafer. But stacking microprocessor chips fabricated with TSVs will require higher alignment precision. A hydrophobic SA technique using the surface tension force generated by the water-to-air interfaces around the pads can greatly reduce the alignment inaccuracy to less than 1 µm. This low-cost and high throughput SA procedure is processed in air, fully-compatible with current fabrication technologies, and highly stable and repeatable. We present a theoretical meniscus model to predict SA results and to provide the design rules. This technique is quite promising for advanced 3D applications involving logic and heterogeneous stacking. As TSVs' dimensions in the chip-level 3D integration are constrained by the chip-level processes, such as bonding, the smallest TSVs might still be about 5 µm. Thus, the area occupied by the TSVs cannot be neglected. Fortunately, TSVs can withstand very high bandwidths, meaning that data can be serialized and transmitted using less numbers of TSVs. With 20 µm TSVs, the 2-Gb/s 8:1 serial link implemented saves 75% of the area of its 8-bit parallel counterpart. The quasi-serial link proposed can effectively balance the inter-layer bandwidth and the serial links' area consumption. The area model of the serial or quasi-serial links working under higher frequencies provides some guidelines to choose the proper serial link design, and it also predicts that when TSV diameter shrinks to 5 µm, it will be difficult to keep this area benefit if without some novel circuit design techniques. As the serial links can be implemented with less area, the bandwidth per unit area is increased. Two scenarios are studied, single-port memory access and multi-port memory access. The expanded inter-layer bandwidth by serialization does not improve the system performance because of the bus-bottleneck problem. In the latter scenario, the inter-layer ultra-wide bandwidth can be exploited as each memory bank can be accessed randomly through the NoC. Thus further widening the inter-layer bandwidth through serialization, the system performance will be improved

MEMS Actuation and Self-Assembly Applied to RF and Optical Devices

The focus of this work involves optical and RF (radio frequency) applications of novel microactuation and self-assembly techniques in MEMS (Microelectromechanical systems). The scaling of physical forces into the micro domain is favorably used to design several types of actuators that can provide large forces and large static displacements at low operation voltages. A self-assembly method based on thermally induced localized plastic deformation of microstructures has been developed to obtain truly three-dimensional structures from a planar fabrication process. RF applications include variable discrete components such as capacitors and inductors as well as tunable coupling circuits. Optical applications include scanning micromirrors with large scan angles (>90 degrees), low operation voltages (<10 Volts), and multiple degrees of freedom. One and two-dimensional periodic structures with variable periods and orientations (with respect to an incident wave) are investigated as well, and analyzed using optical phased array concepts. Throughout the research, permanent tuning via plastic deformation and power-off latching techniques are used in order to demonstrate that the optical and RF devices can exhibit zero quiescent power consumption once their geometry is set