148 research outputs found
On-board processing satellite network architecture and control study
The market for telecommunications services needs to be segmented into user classes having similar transmission requirements and hence similar network architectures. Use of the following transmission architecture was considered: satellite switched TDMA; TDMA up, TDM down; scanning (hopping) beam TDMA; FDMA up, TDM down; satellite switched MF/TDMA; and switching Hub earth stations with double hop transmission. A candidate network architecture will be selected that: comprises multiple access subnetworks optimized for each user; interconnects the subnetworks by means of a baseband processor; and optimizes the marriage of interconnection and access techniques. An overall network control architecture will be provided that will serve the needs of the baseband and satellite switched RF interconnected subnetworks. The results of the studies shall be used to identify elements of network architecture and control that require the greatest degree of technology development to realize an operational system. This will be specified in terms of: requirements of the enabling technology; difference from the current available technology; and estimate of the development requirements needed to achieve an operational system. The results obtained for each of these tasks are presented
Customer premise service study for 30/20 GHz satellite system
Satellite systems in which the space segment operates in the 30/20 GHz frequency band are defined and compared as to their potential for providing various types of communications services to customer premises and the economic and technical feasibility of doing so. Technical tasks performed include: market postulation, definition of the ground segment, definition of the space segment, definition of the integrated satellite system, service costs for satellite systems, sensitivity analysis, and critical technology. Based on an analysis of market data, a sufficiently large market for services is projected so as to make the system economically viable. A large market, and hence a high capacity satellite system, is found to be necessary to minimize service costs, i.e., economy of scale is found to hold. The wide bandwidth expected to be available in the 30/20 GHz band, along with frequency reuse which further increases the effective system bandwidth, makes possible the high capacity system. Extensive ground networking is required in most systems to both connect users into the system and to interconnect Earth stations to provide spatial diversity. Earth station spatial diversity is found to be a cost effective means of compensating the large fading encountered in the 30/20 GHz operating band
EARLY PERFORMANCE PREDICTION METHODOLOGY FOR MANY-CORES ON CHIP BASED APPLICATIONS
Modern high performance computing applications such as personal computing, gaming, numerical simulations require application-specific integrated circuits (ASICs) that comprises of many cores. Performance for these applications depends mainly on latency of interconnects which transfer data between cores that implement applications by distributing tasks. Time-to-market is a critical consideration while designing ASICs for these applications. Therefore, to reduce design cycle time, predicting system performance accurately at an early stage of design is essential. With process technology in nanometer era, physical phenomena such as crosstalk, reflection on the propagating signal have a direct impact on performance. Incorporating these effects provides a better performance estimate at an early stage. This work presents a methodology for better performance prediction at an early stage of design, achieved by mapping system specification to a circuit-level netlist description.
At system-level, to simplify description and for efficient simulation, SystemVerilog descriptions are employed. For modeling system performance at this abstraction, queueing theory based bounded queue models are applied. At the circuit level, behavioral Input/Output Buffer Information Specification (IBIS) models can be used for analyzing effects of these physical phenomena on on-chip signal integrity and hence performance.
For behavioral circuit-level performance simulation with IBIS models, a netlist must be described consisting of interacting cores and a communication link. Two new netlists, IBIS-ISS and IBIS-AMI-ISS are introduced for this purpose. The cores are represented by a macromodel automatically generated by a developed tool from IBIS models. The generated IBIS models are employed in the new netlists. Early performance prediction methodology maps a system specification to an instance of these netlists to provide a better performance estimate at an early stage of design. The methodology is scalable in nanometer process technology and can be reused in different designs
Addressing Manufacturing Challenges in NoC-based ULSI Designs
Hernández Luz, C. (2012). Addressing Manufacturing Challenges in NoC-based ULSI Designs [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/1669
Tester for chosen sub-standard of the IEEE 802.1Q
Tato práce se zabĂ˝vá analyzovánĂm IEEE 802.1Q standardu TSN skupiny a návrhem testovacĂho modulu. TestovacĂ modul je napsán v jazyku VHDL a je moĹľnĂ© jej implementovat do Intel Stratix® V GX FPGA (5SGXEA7N2F45C2) vĂ˝vojovĂ© desky. Standard IEEE 802.1Q (TSN) definuje deterministickou komunikace pĹ™es Ethernet sĂt, v reálnĂ©m ÄŤase, poĹľĂvánĂm globálnĂho ÄŤasu a správnĂ˝m rozvrhem vysĂlánĂm a pĹ™Ăjmem zpráv. HlavnĂ funkce tohoto standardu jsou: ÄŤasová synchronizace, plánovánĂ provozu a konfigurace sĂtÄ›. KaĹľdá z tÄ›chto funkcĂ je definovaná pomocĂ vĂce rĹŻznĂ˝ch podskupin tohoto standardu. Podle definice IEEE 802.1Q standardu je moĹľno tyto podskupiny vzájemnÄ› libovolnÄ› kombinovat. NÄ›kterĂ© podskupiny standardu nemohou fungovat nezávisle, musĂ vyuĹľĂvat funkce jinĂ˝ch podskupin standardu. Realizace funkce podskupin standardu je moĹľná softwarovÄ›, hardwarovÄ›, nebo jejich kombinacĂ. Na základÄ› výše uvedenĂ˝ch fakt, implementace podskupin standardu, kterĂ© jsou softwarovÄ› souvisejĂcĂ, byly vylouÄŤenĂ©. Taky byly vylouÄŤenĂ© podskupiny standardĹŻ, kterĂ© jsou závislĂ© na jinĂ˝ch podskupinách. IEEE 802.1Qbu byl vybrán jako vhodná část pro realizaci hardwarovĂ©ho testu. RĹŻznĂ© zpĹŻsoby testovánĂ byly vysvÄ›tleny jako DFT, BIST, ATPG a dalšà jinĂ© techniky. Pro hardwarovĂ© testovánĂ byla vybrána „Protocol Aware (PA)“technika, protoĹľe tato technika zrychluje testovánĂ, dovoluje opakovanou pouĹľitelnost a taky zkracuje dobu uvedenĂ na trh. TestovacĂ modul se skládá ze dvou objektĹŻ (generátor a monitor), kterĂ© majĂ implementovanou IEEE 802.1Qbu podskupinu standardu. Funkce generátoru je vygenerovat náhodnĂ© nebo nenáhodnĂ© impulzy a potom je poslat do testovanĂ©ho zaĹ™Ăzeni ve správnĂ©m definovanĂ©m protokolu. Funkce monitoru je pĹ™ijat ethernet rámce a ověřit jejich správnost. Objekty jsou navrhnuty stejnĂ˝m zpĹŻsobem na „TOP“úrovni a skládajĂ se ze ÄŤtyĹ™ modulĹŻ: Avalon MM rozhranĂ, dvou šablon a jednoho portu. Avalon MM rozhranĂ bylo vytvoĹ™eno pro komunikaci softwaru s hardwarem. Tento modul pĹ™ijme pakety ze softwaru a potom je dekĂłduje podle definovanĂ©ho protokolu a „pod-protokolu “. „Pod-protokol“se skládá z pĹ™Ăkazu a hodnoty danĂ©ho pĹ™Ăkazu. Podle dekĂłdovanĂ©ho pĹ™Ăkazu a hodnot danĂ˝ch pĹ™Ăkazem je kontrolovanĂ˝ celĂ˝ objekt. Ĺ ablona se pouĹľĂvá na generovánĂ nebo ověřovánĂ náhodnĂ˝ch nebo nenáhodnĂ˝ch dat. DvÄ› šablony byly implementovány pro expresnĂ ověřovánĂ nebo preempÄŤnĂ transakce, definovanĂ© IEEE 802.1Qbu. Porty byly vytvoĹ™enĂ© pro komunikaci mezi testovanĂ˝m zaĹ™ĂzenĂm a šablonou podle danĂ©ho standardu. Port „generátor“má za Ăşkol vybrat a vyslat rámce podle priority a ÄŤasu vysĂlanĂ. Port „monitor“pĹ™ijme rámce do „content-addressable memory”, která ověřuje priority rámce a podle toho je posĂlá do správnĂ© šablony. VĂ˝sledky prokázaly, Ĺľe tato testovacĂ technika dosahuje vysokĂ© rychlosti a rychlĂ© implementace.This master paper is dealing with the analysis of IEEE 802.1Q group of TSN standards and with the design of HW tester. Standard IEEE 802.1Qbu has appeared to be an optimal solution for this paper. Detail explanation of this sub-standard are included in this paper. As HW test the implementation, a protocol aware technique was chosen in order to accelerate testing. Paper further describes architecture of this tester, with detail explanation of the modules. Essential issue of protocol aware controlling objects by SW, have been resolved and described. Result proof that this technique has reached higher speed of testing, reusability, and fast implementation.
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Securing Network Processors with Hardware Monitors
As an essential part of modern society, the Internet has fundamentally changed our lives during the last decade. Novel applications and technologies, such as online shopping, social networking, cloud computing, mobile networking, etc, have sprung up at an astonishing pace. These technologies not only influence modern life styles but also impact Internet infrastructure. Numerous new network applications and services require better programmability and flexibility for network devices, such as routers and switches. Since traditional fixed function network routers based on application specific integrated circuits (ASICs) have difficulty keeping pace with the growing demands of next-generation Internet applications, there is an ongoing shift in the industry toward implementing network devices using programmable network processors (NPs).
While network processors offer great benefits in terms of flexibility, their reprogrammable nature exposes potential security risks. Similar to network end-systems, such as general-purpose computers, software-based network processors have security vulnerabilities that can be attacked remotely. Recent research has shown that a new type of data plane attack is able to modify the functionality of a network processor and cause a denial-of-service (DoS) attack by sending a single malformed UDP packet. Since this attack relies solely on data plane access and does not need access to the control plane, it can be particularly difficult to control.
Hardware security monitors have been introduced to identify and eliminate these malicious packets before they can propagate and cause devastating effects in the network. However, previous work on hardware monitors only focus on single core systems with static (or very slowly changing) workloads. In network processors that use up to hundreds of parallel processor cores and have processing workloads that can change dynamically based on the network traffic, the realization of a complete multicore hardware monitoring system remains a critical challenge. Our research work in this thesis provides a comprehensive solution to this problem.
Our first contribution is the design and prototype implementation of a Scalable Hardware Monitoring Grid (SHMG). This scalable architecture balances area cost and performance overhead by using a clustered approach for multicore NP systems. In order to adapt to dynamically changing network traffic, a resource reallocation algorithm is designed to reassign the processing resources in SHMG to different network applications at runtime. An evaluation of the prototype SHMG on an Altera DE4 board demonstrates low resource and performance overheads. The functionality and performance of a runtime resource reallocation algorithm are tested using a simulation environment.
A second significant contribution of this work is a network system-level security solution for multicore network processors with hardware monitors. It addresses two key problems: (1) how to securely manage and reprogram processor cores and monitors in a deployed router in the network, and (2) how to prevent the large number of identical router devices in the network from an attack that can circumvent one specific monitoring system and lead to Internet-scale failures. A Secure Dynamic Multicore Hardware Monitoring System (SDMMon) is designed based on cryptographic principles and suitable key management to ensure the secure installation of processor binaries and monitor graphs. We present a Merkle tree based parameterizable high performance hash function that can be configured to perform a variety of functions in different devices via a 32-bit configuration parameter. A prototype system composed of both the SDMMon and the parameterizable hash is implemented and evaluated on an Altera DE4 board.
Finally, a fully-functional, comprehensive Multicore NP Security Platform, which integrates both the SHMG and the SDMMon security features, has been implemented on an Altera DE5 board
Broadcast-oriented wireless network-on-chip : fundamentals and feasibility
Premi extraordinari doctorat UPC curs 2015-2016, Ă mbit Enginyeria de les TICRecent years have seen the emergence and ubiquitous adoption of Chip Multiprocessors (CMPs), which rely on the coordinated operation of multiple execution units or cores. Successive CMP generations integrate a larger number of cores seeking higher performance with a reasonable cost envelope. For this trend to continue, however, important scalability issues need to be solved at different levels of design. Scaling the interconnect fabric is a grand challenge by itself, as new Network-on-Chip (NoC) proposals need to overcome the performance hurdles found when dealing with the increasingly variable and heterogeneous communication demands of manycore processors. Fast and flexible NoC solutions are needed to prevent communication become a performance bottleneck, situation that would severely limit the design space at the architectural level and eventually lead to the use of software frameworks that are slow, inefficient, or less programmable.
The emergence of novel interconnect technologies has opened the door to a plethora of new NoCs promising greater scalability and architectural flexibility. In particular, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. Most of the resulting Wireless Network-on-Chip (WNoC) proposals have set the focus on leveraging the latency advantage of this paradigm by creating multiple wireless channels to interconnect far-apart cores. This strategy is effective as the complement of wired NoCs at moderate scales, but is likely to be overshadowed at larger scales by technologies such as nanophotonics unless bandwidth is unrealistically improved.
This dissertation presents the concept of Broadcast-Oriented Wireless Network-on-Chip (BoWNoC), a new approach that attempts to foster the inherent simplicity, flexibility, and broadcast capabilities of the wireless technology by integrating one on-chip antenna and transceiver per processor core. This paradigm is part of a broader hybrid vision where the BoWNoC serves latency-critical and broadcast traffic, tightly coupled to a wired plane oriented to large flows of data. By virtue of its scalable broadcast support, BoWNoC may become the key enabler of a wealth of unconventional hardware architectures and algorithmic approaches, eventually leading to a significant improvement of the performance, energy efficiency, scalability and programmability of manycore chips.
The present work aims not only to lay the fundamentals of the BoWNoC paradigm, but also to demonstrate its viability from the electronic implementation, network design, and multiprocessor architecture perspectives. An exploration at the physical level of design validates the feasibility of the approach at millimeter-wave bands in the short term, and then suggests the use of graphene-based antennas in the terahertz band in the long term. At the link level, this thesis provides an insightful context analysis that is used, afterwards, to drive the design of a lightweight protocol that reliably serves broadcast traffic with substantial latency improvements over state-of-the-art NoCs. At the network level, our hybrid vision is evaluated putting emphasis on the flexibility provided at the network interface level, showing outstanding speedups for a wide set of traffic patterns. At the architecture level, the potential impact of the BoWNoC paradigm on the design of manycore chips is not only qualitatively discussed in general, but also quantitatively assessed in a particular architecture for fast synchronization. Results demonstrate that the impact of BoWNoC can go beyond simply improving the network performance, thereby representing a possible game changer in the manycore era.Avenços en el disseny de multiprocessadors han portat a una Ă mplia adopciĂł dels Chip Multiprocessors (CMPs), que basen el seu potencial en la operaciĂł coordinada de mĂşltiples nuclis de procĂ©s. Generacions successives han anat integrant mĂ©s nuclis en la recerca d'alt rendiment amb un cost raonable. Per a que aquesta tendència continuĂŻ, però, cal resoldre importants problemes d'escalabilitat a diferents capes de disseny. Escalar la xarxa d'interconnexiĂł Ă©s un gran repte en ell mateix, ja que les noves propostes de Networks-on-Chip (NoC) han de servir un trĂ fic eminentment variable i heterogeni dels processadors amb molts nuclis. SĂłn necessĂ ries solucions rĂ pides i flexibles per evitar que les comunicacions dins del xip es converteixin en el pròxim coll d'ampolla de rendiment, situaciĂł que limitaria en gran mesura l'espai de disseny a nivell d'arquitectura i portaria a l'Ăşs d'arquitectures i models de programaciĂł lents, ineficients o poc programables. L'apariciĂł de noves tecnologies d'interconnexiĂł ha possibilitat la creaciĂł de NoCs mĂ©s flexibles i escalables. En particular, la comunicaciĂł intra-xip sense fils ha despertat un interès considerable en virtut de les seva baixa latència, simplicitat, i bon rendiment amb trĂ fic broadcast. La majoria de les Wireless NoC (WNoC) proposades fins ara s'han centrat en aprofitar l'avantatge en termes de latència d'aquest nou paradigma creant mĂşltiples canals sense fils per interconnectar nuclis allunyats entre sĂ. Aquesta estratègia Ă©s efectiva per complementar a NoCs clĂ ssiques en escales mitjanes, però Ă©s probable que altres tecnologies com la nanofotònica puguin jugar millor aquest paper a escales mĂ©s grans. Aquesta tesi presenta el concepte de Broadcast-Oriented WNoC (BoWNoC), un nou enfoc que intenta rendibilitzar al mĂ xim la inherent simplicitat, flexibilitat, i capacitats broadcast de la tecnologia sense fils integrant una antena i transmissor/receptor per cada nucli del processador. Aquest paradigma forma part d'una visiĂł mĂ©s Ă mplia on un BoWNoC serviria trĂ fic broadcast i urgent, mentre que una xarxa convencional serviria fluxos de dades mĂ©s pesats. En virtut de la escalabilitat i del seu suport broadcast, BoWNoC podria convertir-se en un element clau en una gran varietat d'arquitectures i algoritmes poc convencionals que milloressin considerablement el rendiment, l'eficiència, l'escalabilitat i la programabilitat de processadors amb molts nuclis. El present treball tĂ© com a objectius no nomĂ©s estudiar els aspectes fonamentals del paradigma BoWNoC, sinĂł tambĂ© demostrar la seva viabilitat des dels punts de vista de la implementaciĂł, i del disseny de xarxa i arquitectura. Una exploraciĂł a la capa fĂsica valida la viabilitat de l'enfoc usant tecnologies longituds d'ona milimètriques en un futur proper, i suggereix l'Ăşs d'antenes de grafè a la banda dels terahertz ja a mĂ©s llarg termini. A capa d'enllaç, la tesi aporta una anĂ lisi del context de l'aplicaciĂł que Ă©s, mĂ©s tard, utilitzada per al disseny d'un protocol d'accĂ©s al medi que permet servir trĂ fic broadcast a baixa latència i de forma fiable. A capa de xarxa, la nostra visiĂł hĂbrida Ă©s avaluada posant èmfasi en la flexibilitat que aporta el fet de prendre les decisions a nivell de la interfĂcie de xarxa, mostrant grans millores de rendiment per una Ă mplia selecciĂł de patrons de trĂ fic. A nivell d'arquitectura, l'impacte que el concepte de BoWNoC pot tenir sobre el disseny de processadors amb molts nuclis no nomĂ©s Ă©s debatut de forma qualitativa i genèrica, sinĂł tambĂ© avaluat quantitativament per una arquitectura concreta enfocada a la sincronitzaciĂł. Els resultats demostren que l'impacte de BoWNoC pot anar mĂ©s enllĂ d'una millora en termes de rendiment de xarxa; representant, possiblement, un canvi radical a l'era dels molts nuclisAward-winningPostprint (published version
Broadcast-oriented wireless network-on-chip : fundamentals and feasibility
Premi extraordinari doctorat UPC curs 2015-2016, Ă mbit Enginyeria de les TICRecent years have seen the emergence and ubiquitous adoption of Chip Multiprocessors (CMPs), which rely on the coordinated operation of multiple execution units or cores. Successive CMP generations integrate a larger number of cores seeking higher performance with a reasonable cost envelope. For this trend to continue, however, important scalability issues need to be solved at different levels of design. Scaling the interconnect fabric is a grand challenge by itself, as new Network-on-Chip (NoC) proposals need to overcome the performance hurdles found when dealing with the increasingly variable and heterogeneous communication demands of manycore processors. Fast and flexible NoC solutions are needed to prevent communication become a performance bottleneck, situation that would severely limit the design space at the architectural level and eventually lead to the use of software frameworks that are slow, inefficient, or less programmable.
The emergence of novel interconnect technologies has opened the door to a plethora of new NoCs promising greater scalability and architectural flexibility. In particular, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. Most of the resulting Wireless Network-on-Chip (WNoC) proposals have set the focus on leveraging the latency advantage of this paradigm by creating multiple wireless channels to interconnect far-apart cores. This strategy is effective as the complement of wired NoCs at moderate scales, but is likely to be overshadowed at larger scales by technologies such as nanophotonics unless bandwidth is unrealistically improved.
This dissertation presents the concept of Broadcast-Oriented Wireless Network-on-Chip (BoWNoC), a new approach that attempts to foster the inherent simplicity, flexibility, and broadcast capabilities of the wireless technology by integrating one on-chip antenna and transceiver per processor core. This paradigm is part of a broader hybrid vision where the BoWNoC serves latency-critical and broadcast traffic, tightly coupled to a wired plane oriented to large flows of data. By virtue of its scalable broadcast support, BoWNoC may become the key enabler of a wealth of unconventional hardware architectures and algorithmic approaches, eventually leading to a significant improvement of the performance, energy efficiency, scalability and programmability of manycore chips.
The present work aims not only to lay the fundamentals of the BoWNoC paradigm, but also to demonstrate its viability from the electronic implementation, network design, and multiprocessor architecture perspectives. An exploration at the physical level of design validates the feasibility of the approach at millimeter-wave bands in the short term, and then suggests the use of graphene-based antennas in the terahertz band in the long term. At the link level, this thesis provides an insightful context analysis that is used, afterwards, to drive the design of a lightweight protocol that reliably serves broadcast traffic with substantial latency improvements over state-of-the-art NoCs. At the network level, our hybrid vision is evaluated putting emphasis on the flexibility provided at the network interface level, showing outstanding speedups for a wide set of traffic patterns. At the architecture level, the potential impact of the BoWNoC paradigm on the design of manycore chips is not only qualitatively discussed in general, but also quantitatively assessed in a particular architecture for fast synchronization. Results demonstrate that the impact of BoWNoC can go beyond simply improving the network performance, thereby representing a possible game changer in the manycore era.Avenços en el disseny de multiprocessadors han portat a una Ă mplia adopciĂł dels Chip Multiprocessors (CMPs), que basen el seu potencial en la operaciĂł coordinada de mĂşltiples nuclis de procĂ©s. Generacions successives han anat integrant mĂ©s nuclis en la recerca d'alt rendiment amb un cost raonable. Per a que aquesta tendència continuĂŻ, però, cal resoldre importants problemes d'escalabilitat a diferents capes de disseny. Escalar la xarxa d'interconnexiĂł Ă©s un gran repte en ell mateix, ja que les noves propostes de Networks-on-Chip (NoC) han de servir un trĂ fic eminentment variable i heterogeni dels processadors amb molts nuclis. SĂłn necessĂ ries solucions rĂ pides i flexibles per evitar que les comunicacions dins del xip es converteixin en el pròxim coll d'ampolla de rendiment, situaciĂł que limitaria en gran mesura l'espai de disseny a nivell d'arquitectura i portaria a l'Ăşs d'arquitectures i models de programaciĂł lents, ineficients o poc programables. L'apariciĂł de noves tecnologies d'interconnexiĂł ha possibilitat la creaciĂł de NoCs mĂ©s flexibles i escalables. En particular, la comunicaciĂł intra-xip sense fils ha despertat un interès considerable en virtut de les seva baixa latència, simplicitat, i bon rendiment amb trĂ fic broadcast. La majoria de les Wireless NoC (WNoC) proposades fins ara s'han centrat en aprofitar l'avantatge en termes de latència d'aquest nou paradigma creant mĂşltiples canals sense fils per interconnectar nuclis allunyats entre sĂ. Aquesta estratègia Ă©s efectiva per complementar a NoCs clĂ ssiques en escales mitjanes, però Ă©s probable que altres tecnologies com la nanofotònica puguin jugar millor aquest paper a escales mĂ©s grans. Aquesta tesi presenta el concepte de Broadcast-Oriented WNoC (BoWNoC), un nou enfoc que intenta rendibilitzar al mĂ xim la inherent simplicitat, flexibilitat, i capacitats broadcast de la tecnologia sense fils integrant una antena i transmissor/receptor per cada nucli del processador. Aquest paradigma forma part d'una visiĂł mĂ©s Ă mplia on un BoWNoC serviria trĂ fic broadcast i urgent, mentre que una xarxa convencional serviria fluxos de dades mĂ©s pesats. En virtut de la escalabilitat i del seu suport broadcast, BoWNoC podria convertir-se en un element clau en una gran varietat d'arquitectures i algoritmes poc convencionals que milloressin considerablement el rendiment, l'eficiència, l'escalabilitat i la programabilitat de processadors amb molts nuclis. El present treball tĂ© com a objectius no nomĂ©s estudiar els aspectes fonamentals del paradigma BoWNoC, sinĂł tambĂ© demostrar la seva viabilitat des dels punts de vista de la implementaciĂł, i del disseny de xarxa i arquitectura. Una exploraciĂł a la capa fĂsica valida la viabilitat de l'enfoc usant tecnologies longituds d'ona milimètriques en un futur proper, i suggereix l'Ăşs d'antenes de grafè a la banda dels terahertz ja a mĂ©s llarg termini. A capa d'enllaç, la tesi aporta una anĂ lisi del context de l'aplicaciĂł que Ă©s, mĂ©s tard, utilitzada per al disseny d'un protocol d'accĂ©s al medi que permet servir trĂ fic broadcast a baixa latència i de forma fiable. A capa de xarxa, la nostra visiĂł hĂbrida Ă©s avaluada posant èmfasi en la flexibilitat que aporta el fet de prendre les decisions a nivell de la interfĂcie de xarxa, mostrant grans millores de rendiment per una Ă mplia selecciĂł de patrons de trĂ fic. A nivell d'arquitectura, l'impacte que el concepte de BoWNoC pot tenir sobre el disseny de processadors amb molts nuclis no nomĂ©s Ă©s debatut de forma qualitativa i genèrica, sinĂł tambĂ© avaluat quantitativament per una arquitectura concreta enfocada a la sincronitzaciĂł. Els resultats demostren que l'impacte de BoWNoC pot anar mĂ©s enllĂ d'una millora en termes de rendiment de xarxa; representant, possiblement, un canvi radical a l'era dels molts nuclisAward-winningPostprint (published version
Equalized on-chip interconnect : modeling, analysis, and design
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 115-118).This thesis work explores the use of equalization techniques to improve throughput and reduce power consumption of on-chip interconnect. A theoretical model for an equalized on-chip interconnect is first suggested to provide mathematical formulation for the link behavior. Based on the model, a fast-design space exploration methodology is demonstrated to search for the optimal link design parameters (wire and circuit) and to generate the optimal performance-power trade-off curve for the equalized interconnects. This thesis also proposes new circuit techniques, which improve the revealed demerits of the conventional circuit topologies. The proposed charge-injection transmitter directly conducts pre-emphasis current from the supply into the channel, eliminating the power overhead of analog current subtraction in the conventional transmit pre-emphasis, while significantly relaxing the driver coefficient accuracy requirements. The transmitter utilizes a power efficient nonlinear driver by compensating non-linearity with pre-distorted equalization coefficients. A trans-impedance amplifier at the receiver achieves low static power consumption, large signal amplitude, and high bandwidth by mitigating limitations of purely-resistive termination. A test chip is fabricated in 90-nm bulk CMOS technology and tested over a 10 mm, 2[micro]m pitched on-chip differential wire. The transceiver consumes 0.37-0.63 pJ/b with 2-6 Gb/s/ch.by Byungsub Kim.Ph.D
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