Gate Centric Extended Source SOI TFET

An alternative SOI TFET structure precisely GCES SOI TFET has been proposed and studied in this paper by modifying its gate length for three different values. The proposed structure considering point and line tunneling has been derived and validated by simulation. The device is optimized to suitable VDS of 0.1V, extended source alignment with the center position of gate and optimum drain contact position. The transfer characteristics, band diagrams, electric field and potential distributions are examined as the device performance parameter.  The results distinctly exhibit that the device performs best when gate length is 10nm having SS as low as 19.8mV/dec and ratio of ON/OFF current as 1015. SS increases and ON current decreases by a negligible scale when quantum confinement has been taken into account due to discrete energy band at the source channel interface using Schrӧdinger-Poisson model. The simulations are performed using Silvaco, Atlas. Moreover, the GCES SOI TFET inverter is characterized by SPICE calibration, provides a higher gain of 16 at lower VDD=0.2V