237 research outputs found
Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications
Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung
List of symbols and abbreviations
Acknowledgement
1. Introduction
2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias
3. Fabrication of BiCMOS & Silicon Interposer with TSVs
4. Characterization of BiCMOS Embedded Through-Silicon Vias
5. Applications
6. Conclusion and Future Work
7. Appendix
8. Publications & Patents
9. Bibliography
10. List of Figures and Table
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Thermo-mechanical stress measurement and analysis in three dimensional interconnect structures
Three-dimensional (3-D) integration is effective to overcome the wiring limit imposed on device density and performance with continued scaling. The application of TSV (Through-Silicon Via) is essential for 3D IC integration. TSVs are embedded into the silicon substrate to form vertical, electrical connections between stacked IC chips. However, due to the large CTE mismatch between Silicon and Copper, thermal stresses are induced by various thermal histories from the device processing, and they have caused serious concerns regarding the thermal-mechanical reliability.
Firstly, a semi-analytic approach is introduced to understand stress distributions in TSV structures. This is followed by application of finite element analysis for more accurate prediction of stress behavior according to the real geometry of the sample. The conventional Raman method is used to measure the linear combination of in-plane stress components near silicon top surface
Secondly, the limitation of conventional Raman method is discussed: only certain linear combination of in-plane stress, instead of separate value for each stress components, can be obtained. Two different kinds of innovative Raman measurements have been developed and employed to study the normal stress components separately. Both of them take advantages of different laser polarization profiles to resolve the normal stress components separately based on experimental data. The top-down Raman measurements utilize so called “high NA effect” to obtain additional information, and can resolve all 3 normal stress components. Independent bending beam experiments are used to validate the results from cross-section Raman measurement on the same sample. The correlation between top-down Raman measurement and cross-section Raman measurement are investigated as well.
Lastly, as a typical example of 3D IC package, a stack-die memory package is presented. Finite element analysis combined with cross-section Raman measurement and high resolution moiré interferometry were employed to investigate the thermal-mechanical reliability and chip-package interaction of the stack-die memory structure.Physic
Enabling Technologies for 3D ICs: TSV Modeling and Analysis
Through silicon via (TSV) based three-dimensional (3D) integrated circuit (IC) aims to stack and interconnect dies or wafers vertically. This emerging technology offers a promising near-term solution for further miniaturization and the performance improvement of electronic systems and follows a more than Moore strategy. Along with the need for low-cost and high-yield process technology, the successful application of TSV technology requires further optimization of the TSV electrical modeling and design. In the millimeter wave (mmW) frequency range, the root mean square (rms) height of the TSV sidewall roughness is comparable to the skin depth and hence becomes a critical factor for TSV modeling and analysis. The impact of TSV sidewall roughness on electrical performance, such as the loss and impedance alteration in the mmW frequency range, is examined and analyzed following the second order small perturbation method. Then, an accurate and efficient electrical model for TSVs has been proposed considering the TSV sidewall roughness effect, the skin effect, and the metal oxide semiconductor (MOS) effect. However, the emerging application of 3D integration involves an advanced bio-inspired computing system which is currently experiencing an explosion of interest. In neuromorphic computing, the high density membrane capacitor plays a key role in the synaptic signaling process, especially in a spike firing analog implementation of neurons. We proposed a novel 3D neuromorphic design architecture in which the redundant and dummy TSVs are reconfigured as membrane capacitors. This modification has been achieved by taking advantage of the metal insulator semiconductor (MIS) structure along the sidewall, strategically engineering the fixed oxide charges in depletion region surrounding the TSVs, and the addition of oxide layer around the bump without changing any process technology. Without increasing the circuit area, these reconfiguration of TSVs can result in substantial power consumption reduction and a significant boost to chip performance and efficiency. Also, depending on the availability of the TSVs, we proposed a novel CAD framework for TSV assignments based on the force-directed optimization and linear perturbation
Analyse et caractérisation des couplages substrat et de la connectique dans les circuits 3D : Vers des modèles compacts
The 3D integration is the most promising technological solution to track the level of integration dictated by Moore's Law (see more than Moore, Moore versus more). It leads to important research for a dozen years. It can superimpose different circuits and components in one box. Its main advantage is to allow a combination of heterogeneous and highly specialized technologies for the establishment of a complete system, while maintaining a high level of performance with very short connections between the different circuits. The objective of this work is to provide consistent modeling via crossing, and / or contacts in the substrate, with various degrees of finesse / precision to allow the high-level designer to manage and especially to optimize the partitioning between the different strata. This modelization involves the development of multiple views at different levels of abstraction: the physical model to "high level" model. This would allow to address various issues faced in the design process: - The physical model using an electromagnetic simulation based on 2D or 3D ( finite element solver ) is used to optimize the via (materials, dimensions etc..) It determines the electrical performance of the via, including high frequency. Electromagnetic simulations also quantify the coupling between adjacent via. - The analytical compact of via their coupling model, based on a description of transmission line or Green cores is used for the simulations at the block level and Spice type simulations. Analytical models are often validated against measurements and / or physical models.L’intégration 3D est la solution technologique la plus prometteuse pour suivre le niveau d’intégration dictée par la loi de Moore (cf. more than Moore, versus more Moore). Elle entraine des travaux de recherche importants depuis une douzaine d’années. Elle permet de superposer différents circuits et composants dans un seul boitier. Son principal avantage est de permettre une association de technologies hétérogènes et très spécialisées pour la constitution d’un système complet, tout en préservant un très haut niveau de performance grâce à des connexions très courtes entre ces différents circuits. L’objectif de ce travail est de fournir des modélisations cohérentes de via traversant, ou/et de contacts dans le substrat, avec plusieurs degrés de finesse/précision, pour permettre au concepteur de haut niveau de gérer et surtout d’optimiser le partitionnement entre les différentes strates. Cette modélisation passe par le développement de plusieurs vues à différents niveaux d’abstraction: du modèle physique au modèle « haut niveau ». Elle devait permettre de répondre à différentes questions rencontrées dans le processus de conception :- le modèle physique de via basé sur une simulation électromagnétique 2D ou 3D (solveur « éléments finis ») est utilisé pour optimiser l’architecture du via (matériaux, dimensions etc.) Il permet de déterminer les performances électriques des via, notamment en haute fréquence. Les simulations électromagnétiques permettent également de quantifier le couplage entre via adjacents. - le modèle compact analytique de via et de leur couplage, basé sur une description de type ligne de transmission ou noyaux de Green, est utilisé pour les simulations au niveau bloc, ainsi que des simulations de type Spice. Les modèles analytiques sont souvent validés par rapport à des mesures et/ou des modèles physiques
Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling
State-of-the-art devices in the consumer electronics market are relying more and more on Multi-Processor Systems-On-Chip (MPSoCs) as an efficient solution to meet their multiple design constrains, such as low cost, low power consumption, high performance and short time-to-market. In fact, as technology scales down, logic density and power density increase, generating hot spots that seriously affect the MPSoC performance and can physically damage the final system behavior. Moreover, forthcoming three-dimensional (3D) MPSoCs can achieve higher system integration density, but the aforementioned thermal problems are seriously aggravated. Thus, new thermal exploration tools are needed to study the temperature variation effects inside 3D MPSoCs. In this paper, we present a novel approach for fast transient thermal modeling and analysis of 3D MPSoCs with active (liquid) cooling solutions, while capturing the hardware-software interaction. In order to preserve both accuracy and speed, we propose a close-loop framework that combines the use of Field Programmable Gate Arrays (FPGAs) to emulate the hardware components of 2D/3D MPSoC platforms with a highly optimized thermal simulator, which uses an RC-based linear thermal model to analyze the liquid flow. The proposed framework offers speed-ups of more than three orders of magnitude when compared to cycle-accurate 3D MPSoC thermal simulators. Thus, this approach enables MPSoC designers to validate different hardware- and software-based 3D thermal management policies in real-time, and while running real-life applications, including liquid cooling injection contro
Ferrite characterization techniques & particle simulations for semiconductor devices
This dissertation is divided into three papers, covering two major topics. The first topic, techniques for ferrite characterization, is discussed over the course of two papers. The second topic, particle simulations for semiconductor devices, is discussed in the last paper. In the first paper, the method for extracting permeability from ferrite materials is discussed for the Keysight 16454A permeability extraction fixture, where the ferrite material to be characterized is assumed to be homogeneous. Then the method is updated to account for layered materials. The updated method is verified through full-wave simulations. In the second paper, a planar printed circuit board (PCB) coil is proposed as an alternative to the Keysight 16454A fixture for extracting permeability from ferrite materials. The method of extraction is verified through full-wave simulations. The final paper (and second topic) develops a particle simulator, based on the Boltzmann transport equation (BTE) and Monte Carlo (MC) methods, for studying semiconductor devices with submicron feature sizes. Particle simulations are advantageous because full-wave simulators based purely on Maxwell\u27s equations are not able to capture certain semiconductor effects. This work specifically investigates metal-oxide-semiconductor (MOS) effects for a pair of through-silicon-vias (TSVs), and the corresponding accumulation and depletion regions formed for different bias voltages --Abstract, page iv
Thermal-Aware Networked Many-Core Systems
Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors.
This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.Siirretty Doriast
TSV Equivalent Circuit Model using 3D Full-Wave Analysis
This work presents a study to build lumped models for fault-free and faulty Through Silicon Vias (TSVs). Three dimensional full-wave simulations are performed to extract equivalent circuit models. The effects of parametric and catastrophic faults due to pin-holes, voids and open circuits on the equivalent circuit models have been determined through 3D simulations. The extracted TSV models are then used to conduct delay tests to determine the required measurement resolution to detect TSV defects. It is shown that the substrate conductivity has a considerable effect on TSV fault characterization. It is also shown that, regardless of the substrate type, even a relatively large void does not alter the TSV resistance or its parasitic capacitance noticeably at 1GHz solution frequency. An on-chip test solution for TSV parametric faults requires a dedicated high resolution measurement circuit due to the minor variations of TSV circuit model parameters
Multiphysics modeling and simulation for large-scale integrated circuits
This dissertation is a process of seeking solutions to two important and challenging problems related to the design of modern integrated circuits (ICs): the ever increasing couplings among the multiphysics and the large problem size arising from the escalating complexity of the designs. A multiphysics-based computer-aided design methodology is proposed and realized to address multiple aspects of a design simultaneously, which include electromagnetics, heat transfer, fluid dynamics, and structure mechanics. The multiphysics simulation is based on the finite element method for its unmatched capabilities in handling complicate geometries and material properties. The capability of the multiphysics simulation is demonstrated through its applications in a variety of important problems, including the static and dynamic IR-drop analyses of power distribution networks, the thermal-ware high-frequency characterization of through-silicon-via structures, the full-wave electromagnetic analysis of high-power RF/microwave circuits, the modeling and analysis of three-dimensional ICs with integrated microchannel cooling, the characterization of micro- and nanoscale electrical-mechanical systems, and the modeling of decoupling capacitor derating in the power integrity simulations. To perform the large-scale analysis in a highly efficient manner, a domain decomposition scheme, parallel computing, and an adaptive time-stepping scheme are incorporated into the proposed multiphysics simulation. Significant reduction in computation time is achieved through the two numerical schemes and the parallel computing with multiple processors
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