11 research outputs found

    Graphene nano-ribbon and transition metal dichalcogenide field-effect transistor modeling and circuit simulation

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    This dissertation presents a modeling and simulation study of graphene nano-ribbon and transition metal dichalcogenide field-effect transistors. Through compact modeling, SPICE implementation of the transistors is realized, and circuit-level simulation is enabled. Extensive simulation studies are performed to evaluate the performance of these two emerging devices

    Semi-analytical model for carbon nanotube and graphene nanoribbon transistors

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    Carbon nanotubes and graphene provide high carrier mobility for ballistic transport, high carrier velocity for fast switching, and excellent mechanical and thermal conductivity. As a result, they are widely considered as next generation candidate materials for nanoelectronics. In this thesis, I first propose a physics-based semi-analytical model for Schottky-barrier (SB) carbon nanotube (CNT) and graphene nanoribbon (GNR) transistors. The model reduces the computational complexity in the two critical but time-consuming steps, namely the calculation of the tunneling probability and the self-consistent evaluation of the surface potential in the transistor channel. Since SB-type CNT and GNR transistors exhibit ambipolar conduction that is not preferable in digital applications, I further propose a semi-analytical model for the double-gate transistor structure that is able to control the ambipolar conduction in-field. Future directions, including the modeling of new CNT and GNR devices and novel circuits based on the in-field controllability of ambipolar conduction, will also be described

    Novel High Performance Ultra Low Power Static Random Access Memories (SRAMs) Based on Next Generation Technologies

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    Title from PDF of title page viewed January 27, 2021Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (page 107-120)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2019Next Big Thing Is Surely Small: Nanotechnology Can Bring Revolution. Nanotechnology leads the world towards many new applications in various fields of computing, communication, defense, entertainment, medical, renewable energy and environment. These nanotechnology applications require an energy-efficient memory system to compute and process. Among all the memories, Static Random Access Memories (SRAMs) are high performance memories and occupies more than 50% of any design area. Therefore, it is critical to design high performance and energy-efficient SRAM design. Ultra low power and high speed applications require a new generation memory capable of operating at low power as well as low execution time. In this thesis, a novel 8T SRAM design is proposed that offers significantly faster access time and lowers energy consumption along with better read stability and write ability. The proposed design can be used in the conventional SRAM as well as in computationally intensive applications like neural networks and machine learning classifiers [1]-[4]. Novel 8T SRAM design offers higher energy efficiency, reliability, robustness and performance compared to the standard 6T and other existing 8T and 9T designs. It offers the advantages of a 10T SRAM without the additional area, delay and power overheads of the 10T SRAM. The proposed 8T SRAM would be able to overcome many other limitations of the conventional 6T and other 7T, 8T and 9T designs. The design employs single bitline for the write operation, therefore the number of write drivers are reduced. The defining feature of the proposed 8T SRAM is its hybrid design, which is the combination of two techniques: (i) the utilization of single-ended bitline and (ii) the utilization of virtual ground. The single-ended bitline technique ensures separate read and write operations, which eventually reduces the delay and power consumption during the read and write operations. It's independent read and write paths allow the use of the minimum sized access transistors and aid in a disturb-free read operation. The virtual ground weakens the positive feedback in the SRAM cell and improves its write ability. The virtual ground technique is also used to reduce leakages. The proposed design does not require precharging the bitlines for the read operation, which reduces the area and power overheads of the memory system by eliminating the precharging circuit. The design isolates the storage node from the read path, which improves the read stability. For reliability study, we have investigated the static noise margin (SNM) of the proposed 8T SRAM, for which, we have used two methods – (i) the traditional SNM method with the butterfly curve, (ii) the N-curve method A comparative analysis is performed between the proposed and the existing SRAM designs in terms of area, total power consumption during the read and write operations, and stability and reliability. All these advantages make the proposed 8T SRAM design an ideal candidate for the conventional and computationally intensive applications like machine learning classifier and deep learning neural network. In addition to this, there is need for next generation technologies to design SRAM memory because the conventional CMOS technology is approaching its physical and performance boundaries and as a consequence, becoming incompatible with ultra-low-power applications. Emerging devices such as Tunnel Field Effect Transistor (TFET)) and Graphene Nanoribbon Field Effect Transistor (GNRFET) devices are highly potential candidates to overcome the limitations of MOSFET because of their ability to achieve subthreshold slopes below 60 mV/decade and very low leakage currents [6]-[9]. This research also explores novel TFET and GNRFET based 6T SRAM. The thesis evaluates the standby leakage power in the Tunnel FET (TFET) based 6T SRAM cell for different pull-up, pull-down, and pass-gate transistors ratios (PU: PD: PG) and compared to 10nm FinFET based 6T SRAM designs. It is observed that the 10nm TFET based SRAMs have 107.57%, 163.64%, and 140.44% less standby leakage power compared to the 10nm FinFET based SRAMs when the PU: PD: PG ratios are 1:1:1, 1:5:2 and 2:5:2, respectively. The thesis also presents an analysis of the stability and reliability of sub-10nm TFET based 6T SRAM circuit with a reduced supply voltage of 500mV. The static noise margin (SNM), which is a critical measure of SRAM stability and reliability, is determined for hold, read and write operations of the 6T TFET SRAM cell. The robustness of the optimized TFET based 6T SRAM circuit is also evaluated at different supply voltages. Simulations were done in HSPICE and Cadence tools. From the analysis, it is clear that the main advantage of the TFET based SRAM would be the significant improvement in terms of leakage or standby power consumption. Compared to the FinFET based SRAM the standby leakage power of the T-SRAMs are 107.57%, 163.64%, and 140.44% less for 1:1:1, 1:5:2 and 2:5:2 configurations, respectively. Since leakage/standby power is the primary source of power consumption in the SRAM, and the overall system energy efficiency depends on SRAM power consumption, TFET based SRAM would lead to massive improvement of the energy efficiency of the system. Therefore, T-SRAMs are more suitable for ultra-low power applications. In addition to this, the thesis evaluates the standby leakage power of types of Graphene Nanoribbon FETs based 6T SRAM bitcell and compared to 10nm FinFET based 6T SRAM bitcell. It is observed that the 10nm MOS type GNRFET based SRAMs have 16.43 times less standby leakage power compared to the 10nm FinFET based SRAMs. The double gate SB-GNRFET based SRAM consumes 1.35E+03 times less energy compared to the 10nm FinFET based SRAM during write. However, during read double gate SB-GNRFET based SRAM consume 15 times more energy than FinFET based SRAM. It is also observed that GNRFET based SRAMs are more stable and reliable than FinFET based SRAM.Introduction -- Background -- Novel High Performance Ultra Low Power SRAM Design -- Tunnel FET Based SRAM Design -- Graphene Nanoribbon FET Based SRAM Design -- Double-gate FDSOI Based SRAM Designs -- Novel CNTFET and MEMRISTOR Based Digital Designs -- Conclusio

    An Efficient Gate Library for Ambipolar CNTFET Logic

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    Recently, several emerging technologies have been reported as potential candidates for controllable ambipolar devices. Controllable ambipolarity is a desirable property that enables the on-line configurability of n-type and p-type device polarity. In this paper, we introduce a new design methodology for logic gates based on controllable ambipolar devices, with an emphasis on carbon nanotubes as the candidate technology. Our technique results in ambipolar gates with a higher expressive power than conventional complementary metal-oxidesemiconductor (CMOS) libraries. We propose a library of static ambipolar carbon nanotube field effect transistor (CNTFET) gates based on generalized NOR-NAND-AOI-OAI primitives, which efficiently implements XOR-based functions. Technology mapping of several multi-level logic benchmarks that extensively use the XOR function, including multipliers, adders, and linear circuits, with ambipolar CNTFET logic gates indicates that on average, it is possible to reduce the number of logic levels by 42%, the delay by 26%, and the power consumption by 32%, resulting in a energy-delay-product (EDP) reduction of 59% over the same circuits mapped with unipolar CNTFET logic gates. Based on the projections in [1], where it is stated that defectfree CNTFETs will provide a 5Ă— performance improvement over metal-oxide-semiconductor field effect transistors, the ambipolar library provides a performance improvement of 7Ă—, a 57% reduction in power consumption, and a 20Ă— improvement in EDP over the CMOS library

    Variability and reliability analysis of carbon nanotube technology in the presence of manufacturing imperfections

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    In 1925, Lilienfeld patented the basic principle of field effect transistor (FET). Thirty-four years later, Kahng and Atalla invented the MOSFET. Since that time, it has become the most widely used type of transistor in Integrated Circuits (ICs) and then the most important device in the electronics industry. Progress in the field for at least the last 40 years has followed an exponential behavior in accordance with MooreÂżs Law. That is, in order to achieve higher densities and performance at lower power consumption, MOS devices have been scaled down. But this aggressive scaling down of the physical dimensions of MOSFETs has required the introduction of a wide variety of innovative factors to ensure that they could still be properly manufactured. Transistors have expe- rienced an amazing journey in the last 10 years starting with strained channel CMOS transistors at 90nm, carrying on the introduction of the high-k/metal-gate silicon CMOS transistors at 45nm until the use of the multiple-gate transistor architectures at 22nm and at recently achieved 14nm technology node. But, what technology will be able to produce sub-10nm transistors? Different novel materials and devices are being investigated. As an extension and enhancement to current MOSFETs some promising devices are n-type III-V and p-type Germanium FETs, Nanowire and Tunnel FETs, Graphene FETs and Carbon Nanotube FETs. Also, non-conventional FETs and other charge-based information carrier devices and alternative information processing devices are being studied. This thesis is focused on carbon nanotube technology as a possible option for sub-10nm transistors. In recent years, carbon nanotubes (CNTs) have been attracting considerable attention in the field of nanotechnology. They are considered to be a promising substitute for silicon channel because of their small size, unusual geometry (1D structure), and extraordinary electronic properties, including excellent carrier mobility and quasi-ballistic transport. In the same way, carbon nanotube field-effect transistors (CNFETs) could be potential substitutes for MOSFETs. Ideal CNFETs (meaning all CNTs in the transistor behave as semiconductors, have the same diameter and doping level, and are aligned and well-positioned) are predicted to be 5x faster than silicon CMOS, while consuming the same power. However, nowadays CNFETs are also affected by manufacturing variability, and several significant challenges must be overcome before these benefits can be achieved. Certain CNFET manufacturing imperfections, such as CNT diameter and doping variations, mispositioned and misaligned CNTs, high metal-CNT contact resistance, the presence of metallic CNTs (m-CNTs), and CNT density variations, can affect CNFET performance and reliability and must be addressed. The main objective of this thesis is to analyze the impact of the current CNFET manufacturing challenges on multi-channel CNFET performance from the point of view of variability and reliability and at different levels, device and circuit level. Assuming that CNFETs are not ideal or non-homogeneous because of today CNFET manufacturing imperfections, we propose a methodology of analysis that based on a CNFET ideal compact model is able to simulate heterogeneous or non-ideal CNFETs; that is, transistors with different number of tubes that have different diameters, are not uniformly spaced, have different source/drain doping levels, and, most importantly, are made up not only of semiconducting CNTs but also metallic ones. This method will allow us to analyze how CNT-specific variations affect CNFET device characteristics and parameters and CNFET digital circuit performance. Furthermore, we also derive a CNFET failure model and propose an alternative technique based on fault-tolerant architectures to deal with the presence of m-CNTs, one of the main causes of failure in CNFET circuits

    Two-Dimensional Electronics - Prospects and Challenges

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    During the past 10 years, two-dimensional materials have found incredible attention in the scientific community. The first two-dimensional material studied in detail was graphene, and many groups explored its potential for electronic applications. Meanwhile, researchers have extended their work to two-dimensional materials beyond graphene. At present, several hundred of these materials are known and part of them is considered to be useful for electronic applications. Rapid progress has been made in research concerning two-dimensional electronics, and a variety of transistors of different two-dimensional materials, including graphene, transition metal dichalcogenides, e.g., MoS2 and WS2, and phosphorene, have been reported. Other areas where two-dimensional materials are considered promising are sensors, transparent electrodes, or displays, to name just a few. This Special Issue of Electronics is devoted to all aspects of two-dimensional materials for electronic applications, including material preparation and analysis, device fabrication and characterization, device physics, modeling and simulation, and circuits. The devices of interest include, but are not limited to transistors (both field-effect transistors and alternative transistor concepts), sensors, optoelectronics devices, MEMS and NEMS, and displays

    Electronic Nanodevices

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    The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications

    Theory, Modelling and Implementation of Graphene Field-Effect Transistor

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    PhDTwo-dimensional materials with atomic thickness have attracted a lot of attention from researchers worldwide due to their excellent electronic and optical properties. As the silicon technology is approaching its limit, graphene with ultrahigh carrier mobility and ultralow resistivity shows the potential as channel material for novel high speed transistor beyond silicon. This thesis summarises my Ph.D. work including the theory and modelling of graphene field-effect transistors (GFETs) as well as their potential RF applications. The introduction and review of existing graphene transistors are presented. Multiscale modelling approaches for graphene devices are also introduced. A novel analytical GFET model based on the drift-diffusion transport theory is then developed for RF/microwave circuit analysis. Since the electrons and holes have different mobility variations against the channel potential in graphene, the ambipolar GFET cannot be modelled with constant carrier mobility. A new carrier mobility function, which enables the accurate modelling of the ambipolar property of GFET, is hence developed for this purpose. The new model takes into account the carrier mobility variation against the bias voltage as well as the mobility difference between electrons and holes. It is proved to be more accurate for the DC current calculation. The model has been written in Verilog-A language and can be import into commercial software such as Keysight ADS for circuit simulation. In addition, based on the proposed model two GFET non-Foster circuits (NFCs) are conducted. As a negative impedance element, NFCs find their applications in impedance matching of electrically small antennas and bandwidth improvement of metasurfaces. One of the NFCs studied in this thesis is based on the Linvill's technique in which a pair of identical GFETs is used while the other circuit utilises the negative resistance of a single GFET. The stability analysis of NFCs is also presented. Finally, a high impedance surface loaded with proposed NFCs is also studied, demonstrating significant bandwidth enhancement.Engineering and Physical Sciences Research Council (EPSRC) Grant on `Graphene Flexible Electronics and Optoelectronics' (EP/K01711X/1), the EU Graphene Flagship (FP7-ICT-604391) and Graphene Core 1 (H2020 696656
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