Analytical Probability Density Calculation of Power-Supply-Induced Jitter in high-speed Tx circuits

Department of Electrical EngineeringAs the speed of I/O interface has increased up to multi-gigabit data rates [1], the research of signal integrity issues for the I/O channel is more demanding. The statistical approach to get jitter in time domain can reduce computational time and effort compared to the typical transient SPICE simulations. In this paper, the output voltage waveforms of the multi-stage buffers are calculated with simpler analytical solutions. The driving non-linear MOSFETs are replaced by Thevenin equivalent voltages and impedances, and the solutions of differential equations can be simply expressed with corresponding impulse responses. Also, the jitter induced by the supply voltage fluctuations can be calculated. The supply voltage fluctuations in the time domain are directly convolved with the impulse responses to obtain the output waveforms. The validation of the proposed analytic method is done by experiments. In the experiments, the voltage fluctuations in time domain are measured both at the integrated circuit (IC) and printed circuit board (PCB) pads simultaneously. Then, the on-chip supply voltage fluctuations are extracted from the measured results. The Power Distribution Network (PDN) of the IC and PCB are modeled from impedance measurements on the pads. Using the PDN model, the measured power and ground voltage fluctuations are validated with the SPICE simulation. The output off-chip channel of the victim buffer can be modeled as parasitic inductances and capacitances from the measured two-port S-parameters at the designed PCB channel. As the number of buffer stages connected to the fluctuating supply voltages are varied from one to three in the experiments, the effect on the output waveform induced by supply voltage fluctuations can be investigated. The calculated step responses and jitter PDFs of the multi-stage buffers are all validated with measured output waveforms and jitter histograms. In addition, the Electrostatic discharge (ESD) protection structures which are commonly employed at near the I/O pins can induce parasitic junction capacitance (CESD) and parasitic resistance (RESD) causing parasitic effects. Thus, the supply voltage fluctuations also can couple through ESD parasitic. The step responses of a linear output driver with silicon interposer channel are derived including the parasitics of ESD protection circuits. The probability density functions of the output voltage due to supply voltage fluctuations are also analytically calculated. With changing the frequency of supply voltage fluctuations, the effect of ESD parasitics on the output jitter is calculated and compared.ope

Analog dithering techniques for highly linear and efficient transmitters

The current thesis is about investigation of new methods and techniques to be able to utilize the switched mode amplifiers, for linear and efficient applications. Switched mode amplifiers benefit from low overlap between the current and voltage wave forms in their output terminals, but they seriously suffer from nonlinearity. This makes it impossible to use them to amplify non-constant envelope message signals, where very high linearity is expected. In order to do that, dithering techniques are studied and a full linearity analysis approach is developed, by which the linearity performance of the dithered amplifier can be analyzed, based on the dithering level and frequency. The approach was based on orthogonalization of the equivalent nonlinearity and is capable of prediction of both co-channel and adjacent channel nonlinearity metrics, for a Gaussian complex or real input random signal. Behavioral switched mode amplifier models are studied and new models are developed, which can be utilized to predict the nonlinear performance of the dithered power amplifier, including the nonlinear capacitors effects. For HFD application, self-oscillating and asynchronous sigma delta techniques are currently used, as pulse with modulators (PWM), to encode a generic RF message signal, on the duty cycle of an output pulse train. The proposed models and analysis techniques were applied to this architecture in the first phase, and the method was validated with measurement on a prototype sample, realized in 65 nm TSMC CMOS technology. Afterwards, based on the same dithering phenomenon, a new linearization technique was proposed, which linearizes the switched mode class D amplifier, and at the same time can reduce the reactive power loss of the amplifier. This method is based on the dithering of the switched mode amplifier with frequencies lower than the band-pass message signal and is called low frequency dithering (LFD). To test this new technique, two test circuits were realized and the idea was applied to them. Both of the circuits were of the hard nonlinear type (class D) and are integrated CMOS and discrete LDMOS technologies respectively. The idea was successfully tested on both test circuits and all of the linearity metric predictions for a digitally modulated RF signal and a random signal were compared to the measurements. Moreover a search method to find the optimum dither frequency was proposed and validated. Finally, inspired by averaging interpretation of the dithering phenomenon, three new topologies were proposed, which are namely DLM, RF-ADC and area modulation power combining, which are all nonlinear systems linearized with dithering techniques. A new averaging method was developed and used for analysis of a Gilbert cell mixer topology, which resulted in a closed form relationship for the conversion gain, for long channel devices

Disseny microelectrnic de circuits discriminadors de polsos pel detector LHCb

The aim of this thesis is to present a solution for implementing the front end system of the Scintillator Pad Detector (SPD) of the calorimeter system of the LHCb experiment that will start in 2008 at the Large Hadron Collider (LHC) at CERN. The requirements of this specific system are discussed and an integrated solution is presented, both at system and circuit level. We also report some methodological achievements. In first place, a method to study the PSRR (and any transfer function) in fully differential circuits taking into account the effect of parameter mismatch is proposed. Concerning noise analysis, a method to study time variant circuits in the frequency domain is presented and justified. This would open the possibility to study the effect of 1/f noise in time variants circuits. In addition, it will be shown that the architecture developed for this system is a general solution for front ends in high luminosity experiments that must be operated with no dead time and must be robust against ballistic deficit

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Analysis and Design of High Speed Serial Interfaces for Automotive Applications

The demand for an enriched end-user experience and increased performance in next generation electronic applications is never ending, and it is a common trend for a wide spectrum of applications owing to different markets, like computing, mobile communication and automotive. For this reason High Speed Serial Interface have become widespread components for nowadays electronics with a constant demand for power reduction and data rate increase. In the frame of gigabit serial systems, the work discussed in this thesis develops in two directions: on one hand, the aim is to support the continuous data rate increase with the development of novel link modeling approaches that will be employed for system level evaluation and as support in the design and characterization phases. On the other hand, the design considerations and challenges in the implementation of the transmitter, one of the most delicate blocks for the signal integrity performance of the link, are central. The first part of the activity regarding link performance predictions lead to the development of an enhanced statistical simulation approach, capable to account for the transmitter waveform shape in the ISI analysis, a characteristic that is missed by the available state-ofthe- art simulation approaches. The proposed approach has been extensively tested by comparison with traditional simulation approaches (Spice-like simulators) and validated against experimental characterization of a test system, with satisfactory results. The second part of the activity consists in the design of a high speed transmitter in a deeply scaled CMOS technology, spanning from the concept of the circuit, its implementation and characterization. Targets of the design are to achieve a data rate of 5 Gb/s with a minimum voltage swing of 800 mV, thus doubling the data rate of the current transmitter implementation, and reduce the power dissipation adopting a voltage mode architecture. The experimental characterization of the fabricated lot draws a twofold picture, with some of the performance figures showing a very good qualitative and quantitative agreement with pre-silicon simulations, and others revealing a poor performance level, especially for the eye diagram. Investigation of the root causes by the analysis of the physical silicon design, of the bonding scheme of the prototypes and of the pre-silicon simulations is reported. Guidelines for the redesign of the circuit are also given.Nel panorama delle applicazioni elettroniche il miglioramento delle performance di un prodotto da una generazione alla successiva ha lo scopo di offrire all\u2019utilizzatore finale nuove funzioni e migliorare quelle esistenti. Negli ultimi anni grazie al costante avanzamento della tecnologia integrata, si \ue8 assistito ad un enorme sviluppo della capacit\ue0 computazionale dei dispositivi in tutti i segmenti di mercato, quali ad esempio l\u2019information technology, la comunicazione mobile e l\u2019automotive. La conseguente necessit\ue0 di mettere in comunicazione dispostivi diversi all\u2019interno della stessa applicazione e di traferire grosse quantit\ue0 di dati ha provocato una capillare diffusione delle interfacce seriali ad alta velocit\ue0, o High Speed Serial Interfaces (HSSIs). La necessit\ue0 di ridurre il consumo di potenza e aumentare il bit rate per questo tipo di applicazioni \ue8 diventata dunque un ambito di ricerca di estremo interesse. Il lavoro discusso in questa tesi si colloca nell\u2019ambito della trasmissione di dati seriali a bit rate superiori ad 1Gb/s e si sviluppa in due direzioni: da un lato, a sostegno del continuo aumento del bit rate nelle nuove generazioni di interfacce, \ue8 stato affrontato lo sviluppo di nuovi approcci di modellazione del sistema, che possano essere impiegati nella valutazione delle prestazioni dell\u2019interfaccia e a supporto delle fasi di progettazione e di caratterizzazione. Dall\u2019altro lato, si \ue8 focalizzata l\u2019attenzione sulle sfide e sulle problematiche inerenti il progetto di uno dei blocchi pi\uf9 delicati per le prestazioni del sistema, il trasmettitore. La prima parte della tesi ha come oggetto lo sviluppo di un approccio di simulazione statistico innovativo, in grado di includere nell\u2019analisi degli effetti dell\u2019interferenza di intersimbolo anche la forma d\u2019onda prodotta all\u2019uscita del trasmettitore, una caratteristica che non \ue8 presente in altri approcci di simulazione proposti in letteratura. La tecnica proposta \ue8 ampiamente testata mediante il confronto con approcci di simulazione tradizionali (di tipo Spice) e mediante il confronto con la caratterizzazione sperimentale di un sistema di test, con risultati pienamente soddisfacenti. La seconda parte dell\u2019attivit\ue0 riguarda il progetto di un trasmettitore integrato high speed in tecnologia CMOS a 40nm e si estende dallo studio di fattibilit\ue0 del circuito fino alla sua realizzazione e caratterizzazione. Gli obiettivi riguardano il raggiungimento di un bit rate pari a 5 Gb/s, raddoppiando cos\uec il bit rate dell\u2019attuale implementazione, e di una tensione differenziale di uscita minima di 800mV (picco-picco) riducendo allo stesso tempo la potenza dissipata mediante l\u2019adozione di una architettura Voltage Mode. I risultati sperimentali ottenuti dal primo lotto fabbricato non delineano un quadro univoco: alcune performance mostrano un ottimo accordo qualitativo e quantitativo con le simulazioni pre-fabbricazione, mentre prestazioni non soddisfacenti sono state ottenute in particolare per il diagramma ad occhio. Grazie all\u2019analisi del layout del prototipo, del bonding tra silicio e package e delle simulazioni pre-fabbricazione \ue8 stato possibile risalire ai fattori responsabili del degrado delle prestazioni rispetto alla previsioni pre-fabbricazione, permettendo inoltre di delineare le linee guida da seguire nella futura progettazione di un nuovo prototipo

Studies and development of a readout ASIC for pixelated CdTe detectors for space applications

Le travail présenté dans ce manuscrit a été effectué au sein de l équipe de microélectronique de l Institut de Recherche sur les lois Fondamentales de l Univers (IRFU) du CEA. Il s inscrit dans le contexte de la spectro-imagerie X et gamma pour la recherche en Astrophysique. Dans ce domaine, les futures expériences embarquées à bords de satellites nécessiteront des instruments d imagerie à très hautes résolutions spatiales et énergétiques.La résolution spectrale d une gamma-camera est dégradée par l imperfection du détecteur lors de l interaction photon-matière lui-même et par le bruit électronique. Si on ne peut réduire l imprécision de conversion photon-charge du détecteur, on peut minimiser le bruit apporté par l électronique de lecture. L objectif de cette thèse est la conception d une électronique intégrée de lecture de détecteur semi-conducteurs CdTe pixélisés pour gamma-caméra(s) compacte(s) et aboutable(s) sur 4 côtés à résolution spatiale Fano limitée . Les objectifs principaux de ce circuit intégré sont: un très bas bruit pour la mesure d énergie des rayons-X, une très basse consommation, et une taille de canal de détection adaptée au pas des pixels CdTe. Pour concevoir une telle électronique, chaque paramètre contribuant au bruit doit être optimisé. L hybridation entre l électronique de lecture et le détecteur est également un paramètre clef qui fait généralement la résolution finale de l instrument : en imposant une géométrie matricielle à l ASIC adaptée au pas de 300 m des pixels de CdTe, on peut espérer, réduire d un facteur 10 la capacité parasite amenée par la connexion détecteur-électronique et améliorer d autant le bruit électronique tout en conservant une densité de puissance constante. Une bonne connaissance des propriétés du détecteur nous permet alors d extraire ses paramètres électroniques clefs pour concevoir l architecture électronique de conversion et de filtrage optimale. Dans le cadre de cette thèse j ai conçu deux circuits intégrés en technologies CMOS XFAB 0.18 m. Le premier, Caterpylar, est destiné à caractériser cette nouvelle technologie, y compris en radiation, identifier un étage d entrée pour le pixel adapté au détecteur, et valider par la mesure les résultats théoriques établis sur deux architectures de filtrage, semi gaussien et Multi-Correlated Double Sampling (MCDS), approchant l efficacité du filtrage optimal et adaptées aux applications finales. Le deuxième circuit, D2R1, est un système complet, constitué de 256 canaux de lecture de détecteur CdTe, organisés dans une matrice de 16.16 pixels. Chaque canal comprend un préamplificateur de charge adapté à des pixels de 300 m.300 m, un opérateur de filtrage de type MCDS de profondeur programmable, d un discriminateur auto-déclenché à bas seuil de détection programmable par canal. L ASIC a été caractérisé sans détecteur et est en voie d être hybridé à une matrice de CdTe très prochainement. Les résultats de caractérisations de la puce nue, en particulier en terme de produit puissance . bruit, sont excellents. La consommation de la puce est de 315 W/ canal, la charge équivalente de bruit mesurée sur tous les canaux est de 29 électrons rms. Ces résultats valident le choix d intégration d un filtrage de type MCDS, qui est, à notre connaissance une première mondiale pour la lecture de détecteurs CdTe. Par ailleurs, ils nous permettent d envisager d excellentes résolutions spectrales de l ensemble détecteur+ASIC, de l ordre de 600 eV FWHM à 60 keV.The work presented in this thesis is part of a project where a new instrument is developed: a camera for hard X-rays imaging spectroscopy. It is dedicated to fundamental research for observations in astrophysics, at wavelengths which can only be observed using space-borne instruments. In this domain the spectroscopic accuracy as well as the imaging details are of high importance. This work has been realized at CEA/IRFU (Institut de Recherche sur les lois Fondamentales de l Univers), which has a long-standing and successful experience in instruments for high energy physics and space physics instrumentation. The objective of this thesis is the design of the readout electronics for a pixelated CdTe detector, suitable for a stacked assembly. The principal parameters of this integrated circuit are a very low noise for reaching a good accuracy in X-ray energy measurement, very low power consumption, a critical parameter in space-borne applications, and a small dead area for the full system combining the detector and the readout electronics. In this work I have studied the limits of these three parameters in order to optimize the circuit.In terms of the spectral resolution, two categories of noise had to be distinguished to determine the final performance. The first is the Fano noise limit. related to detector interaction statistics, which cannot be eliminated. The second is the electronic noise, also unavoidable; however it can be minimized through optimization of the detection chain. Within the detector, establishing a small pixel pitch of 300 m reduces the input capacitance and the dark current. This limits the effects of the electronic noise. Also in order to limit the input capacitance the future camera is designed as a stacked assembly of the detector with the readout ASIC. This allows to reach extremely good input parameters seen by the readout electronics: a capacitance in range of 0.3 pF - 1 pF and a dark current below 5 pA.In the frame of this thesis I have designed two ASICs. The first one, Caterpylar, is a testchip, which enables the characterization of differently dimensioned CSA circuits to choose the most suitable one for the final application. It is optimized for readout of the target CdTe detector with 300 m pixel pitch and the corresponding input parameters. With this circuit I have also analyzed possible filtering methods, in particular the semi-Gaussian shaping and the Multi-Correlated Double Sampling (MCDS). Their comparison is preceded by the theoretical analysis of these shapers. The second ASIC D2R1 is a complete readout circuit, containing 256 channels to readout CdTe detector with the same number of pixels, arranged in 16.16 array. Each channel fits into a layout area of 300 m . 300 m. It is based on the MCDS processing with self-triggering capabilities. The mean electronic noise measured over all channels is 29 electrons rms when characterized without the detector. The corresponding power consumption is 315 W channel. With these results the future measurements with the detector give prospects for reaching an FWHM spectral resolution in the order of 600 eV at 60 keV.PARIS11-SCD-Bib. électronique (914719901) / SudocSudocFranceF

The STiC ASIC High Precision Timing with Silicon Photomultipliers

In recent years, Silicon Photomultipliers are being increasingly used for Time of Flight measurements in particle detectors. To utilize the high intrinsic time resolution of these sensors in detector systems, the development of specialized, highly integrated readout electronics is required. In this thesis, a mixed-signal application specific integrated circuit, named STiC, has been developed, characterized and integrated in a detector system. STiC has been specifically designed for high precision timing measurements with SiPMs, and is in particular dedicated to the EndoTOFPET-US project, which aims to achieve a coincidence time resolution of 200 ps FWHM and an energy resolution of less than 20% in an endoscopic positron emission tomography system. The chip integrates 64 high precision readout channels for SiPMs together with a digital core logic to process, store and transfer the recorded events to a data acquisition system. The performance of the chip has been validated in coincidence measurements using detector modules consisting of 3.1×3.1×15 mm³ LYSO crystals coupled to Silicon Photomultipliers from Hamamatsu. The measurements show an energy resolution of 15% FWHM for the detection of 511keV photons. A coincidence time resolution of 213ps FWHM has been measured, which is among the best resolution values achieved to date with this detector topology. STiC has been integrated in the EndoTOFPET-US detector system and has been chosen as the baseline design for the readout of SiPM sensors in the Mu3e experiment

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

High-Speed Wide-Field Time-Correlated Single-Photon Counting Fluorescence Lifetime Imaging Microscopy

Fluorescence microscopy is a powerful imaging technique used in the biological sciences to identify labeled components of a sample with specificity. This is usually accomplished through labeling with fluorescent dyes, isolating these dyes by their spectral signatures with optical filters, and recording the intensity of the fluorescent response. Although these techniques are widely used, fluorescence intensity images can be negatively affected by a variety of factors that impact the fluorescence intensity. Fluorescence lifetime imaging microscopy (FLIM) is an imaging technique that is relatively immune to intensity fluctuations and also provides the unique ability to directly monitor the microenvironment surrounding a fluorophore. Despite the benefits associated with FLIM, the applications to which it is applied are fairly limited due to long image acquisition times and high cost of traditional hardware. Recent advances in complementary metal-oxide-semiconductor (CMOS) single-photon avalanche diodes (SPADs) have enabled the design of low-cost imaging arrays that are capable of recording lifetime images with acquisition times greater than one order of magnitude faster than existing systems. However, these SPAD arrays have yet to realize the full potential of the technology due to limitations in their ability to handle the vast amount of data generated during the commonly used time-correlated single-photon counting (TCSPC) lifetime imaging technique. This thesis presents the design, implementation, characterization, and demonstration of a high speed FLIM imaging system. The components of this design include a CMOS imager chip in a standard 0.13 μm technology containing a custom CMOS SPAD, a 64-by-64 array of these SPADs, pixel control circuitry, independent time-to-digital converters (TDCs), a FLIM specific datapath, and high bandwidth output buffers. In addition to the CMOS imaging array, a complete system was designed and implemented using a printed circuit board (PCB) for capturing data from the imager, creating histograms for the photon arrival data using field-programmable gate arrays, and transferring the data to a computer using a cabled PCIe interface. Finally, software is used to communicate between the imaging system and a computer.The dark count rate of the SPAD was measured to be only 231 Hz at room temperature while maintaining a photon detection probability of up to 30\%. TDCs included on the array have a 62.5 ps resolution and a 64 ns range, which is suitable for measuring the lifetime of most biological fluorophores. Additionally, the on-chip datapath was designed to handle continuous data transfers at rates capable of supporting TCSPC-based lifetime imaging at 100 frames per second. The system level implementation also provides sufficient data throughput for transferring up to 750 frames per second from the imaging system to a computer. The lifetime imaging system was characterized using standard techniques for evaluating SPAD performance and an electrical delay signal for measuring the TDC performance. This thesis concludes with a demonstration of TCSPC-FLIM imaging at 100 frames per second -- the fastest 64-by-64 TCSPC FLIM that has been demonstrated. This system overcomes some of the limitations of existing FLIM systems and has the potential to enable new application domains in dynamic FLIM imaging

Developments toward a Silicon Strip Tracker for the PANDA Experiment

The PANDA detector at the future FAIR facility in Darmstadt will be a key experiment in the understanding of the strong interaction at medium energies where perturbative models fail to describe the quark-quark interaction. An important feature of the detector system is the ability to reconstruct secondary decay vertices of short-lived intermediate states by means of a powerful particle tracking system with the the Micro-Vertex Detector (MVD) as central element to perform high-resolution charmonium and open-charm spectroscopy. The MVD is conceived with pixel detectors in the inner parts and double-sided silicon strip detectors at the outer half in a very lightweight design. The PANDA detector system shall be operated in a self-triggering broadband acquisition mode. Implications on the read-out electronics and the construction of the front-end assemblies are analyzed and evaluation of prototype DSSD-detectors wrt. signal-to-noise ratio, noise figures, charge sharing behavior, spacial resolution and radiation degradation discussed. Methods of electrical sensor characterization with different measurement setups are investigated which may be useful for future large-scale QA procedures. A novel algorithm for recovering multiple degenerate cluster hit patterns of double-sided strip sensors is introduced and a possible architecture of a Module Data Concentrator ASIC (MDC) aggregating multiple front-end data streams conceived. A first integrative concept for the construction and assembly of DSSD modules for the barrel part of the MVD is introduced as a conclusion of the thesis. Furthermore, a detailed description of a simplified procedure for the calculation of displacement damage in compound materials is given as reference which was found useful for the retrieval of non-ionizing energy loss for materials other than silicon.Der PANDA Detektor im zukünftigen FAIR-Beschleunigerkomplex in Darmstadt wird ein Schlüsselexperiment im Verständnis der starken Wechselwirkung bei mittleren Energien, bei denen kein Zugang über perturbative Methoden zur Quark-Quark Interaktion existiert, sein. Eine wichtige Eigenschaft des Detektorsystems, die Ortsrekonstruktion sekundärer Zerfallsvertizes kurzlebiger Zwischenzustände, wird dabei durch ein Spurverfolgungssystem mit dem Mikro-Vertex Detektor (MVD) als wichtigstem Element zur hochauflösenden Charmoniumund Open-Charm Spektroskopie garantiert. Der MVD ist konzipiert als leichtgewichtiges, geteiltes Silizium-Detektorsystem mit Pixeldetektoren im inneren Bereich und doppelseitigen Streifendetektoren (DSSD) in den äußeren Regionen. Das PANDA Detektorsystem soll in einem selbstgetriggertem Regime Daten breitbandig und ohne Totzeitverluste verarbeiten können. Die sich daraus ergebenden Implikationen auf den Aufbau der Ausleseelektronik und der Front-end-Baugruppen werden analysiert und es werden Ergebnisse von Messungen an DSSD-Prototypen im Hinblick auf Signal-zu-Rausch-Verhältnis, Rauscheigenschaften, Ladungsteilungsverhalten, Ortsauflösung und Bestrahlungstoleranz diskutiert. Methoden zur elektrischen Charakterisierung von Sensoren werden untersucht, die bei zukünftigen großangelegten QA-Untersuchungen nützlich eingesetzt werden können. Ein neuartiger Cluster- Korrelationsalgorithmus, welcher mehrfach entartete Clusterhit-Muster zu erkennen vermag wird ebenso vorgestellt wie eine mögliche Architektur des noch zu entwickelnden Module-Data- Concentrator ASIC (MDC), welcher die Datenströme der Front-end Chips auf Modulebene zusammenfassen soll. Ein erstes integratives Konzept für Konstruktion und Zusammenbau von DSSD-Modulen des Barrel-Bereichs des MVD wird im Abschluss der Dissertation vorgestellt. Darüber hinaus wird eine detaillierte Beschreibung einer vereinfachten Vorschrift zur Berechnung des Versetzungsschadens durch Neutronen in zusammengesetzten Stoffen angegeben, welche sich als nützlich für die Ableitung des nicht-ionisierenden Energieverlustes in Materialien neben Silizium erwiesen hat