Compact DC Modelling of Short-Channel Effects in Organic Thin-Film Transistors

Els transistors orgànics de capa fina (TFT) són dispositius prometedors per a les pantalles flexibles de matriu activa i els conjunts de sensors, ja que poden fabricar-se a temperatures de procés relativament baixes i, per tant, no sols en vidre, sinó també en substrats polimèrics. Per a millorar el rendiment dinàmic dels dispositius i circuits TFT , una reducció agressiva de la longitud de canal provoca efectes extrínsecs en els dispositius que han de ser capturats per models compactes. Aquesta tesi presenta models analítics, basats en la física, de la degradació de la pendent subumbral, el roll-off del voltatge llindar i l'efecte DIBL en TFTs coplanars i escalonats que poden ser implementats en qualsevol model compacte de corrent continu arbitrari que estigui definit pel voltatge llindar i la pendent subumbral. Per tant, l'equació diferencial de Laplace es resol per a la geometria coplanar i escalonada aplicant la transformación Schwarz-Cristoffel. Les solucions del potencial serveixen de base per a la definició de les equacions del model. A més, es desenvolupen models compactes de les barreres Schottky dependents de la polarització en les interfícies font/semiconductor i drenador/semiconductor en els TFT coplanars i escalonats, que modelen la injecció i l'ejecció de portadors de càrrega, respectivament, com a corrent d'emissió termoiònica.Los transistores orgánicos de capa fina (TFT) son dispositivos prometedores para las pantallas flexibles de matriz activa y los conjuntos de sensores, ya que pueden fabricarse a temperaturas de proceso relativamente bajas y, por tanto, no sólo en vidrio, sino también en sustratos poliméricos. Para mejorar el rendimiento dinámico de los dispositivos y circuitos TFT, una reducción agresiva de la longitud de los canales provoca efectos extrínsecos en los dispositivos que tienen que ser capturados por modelos compactos. Esta tesis presenta modelos analíticos, basados en la física, de la degradación de la pendiente subumbral, el roll-off del voltaje umbral y el efecto DIBL en TFTs coplanares y escalonados que pueden ser implementados en cualquier modelo compacto de corriente continua arbitrario que esté definido por el voltaje umbral y la pendiente subumbral. Por lo tanto, la ecuación diferencial de Laplace se resuelve para la geometría coplanar y escalonada aplicando la transformación Schwarz-Christoffel. Las soluciones del potencial sirven de base para la definición de las ecuaciones del modelo. Además, se desarrollan modelos compactos de las barreras Schottky dependientes de la polarización en las interfaces fuente/semiconductor y drenador/semiconductor en los TFT coplanares y escalonados, que modelan la inyección y la eyección de portadores de carga, respectivamente, como corriente de emisión termoiónicaOrganic thin-film transistors (TFTs) are promising devices for flexible active-matrix displays and sensor arrays, since they can be fabricated at relatively low process temperatures and thus not only on glass, but also on polymeric substrates. In order to improve the dynamic TFT and circuit performance, an aggressive reduction of the channel length causes extrinsic de-vice effects that have to be captured by compact models. This dissertation presents analytical, physics-based models of the subthreshold-swing degra-dation, the thresholdvoltage roll-off and DIBL effects in coplanar and staggered TFTs that can be implemented in any arbitrary compact dc model that are defined by the threshold voltage and the subthreshold swing. Therefore, Laplace’s differential equation is solved for the coplanar and staggered geometry by applying the Schwarz-Christoffel transformation. The potential solutions serve as a basis for the definition of the model equations. Further-more, compact models of the biasdependent Schottky barriers at the source/semiconductor and drain/semiconductor interfaces in coplanar and staggered TFTs are derived, which model the charge carriers injection and ejection, respectively, as thermionic emission cur-rent. Thereby, in case of the source barrier, the Schottky barrier lowering effect due to im-age charges is captured and therefore, an analytical expression of the electric field at the source barrier is derived

Charge-Based Compact Modeling of Capacitances and Low-Frequency Noise in Organic Thin-Film Transistors

Els transistors orgànics de capa prima són candidats prometedors per a noves aplicacions electròniques a causa de la possibilitat de fabricar dispositius electrònics orgànics a baixes temperatures sobre substrats flexibles com el plàstic o el paper. Aquesta tesi doctoral tracta del desenvolupament d'un model compacte basat en la càrrega per a la descripció del comportament capacitiu i del soroll de baixa freqüència en transistors orgànics de capa prima. A partir d'un model de corrent continu existent, es deriven expressions per a les càrregues totals en condicions d'operació quasi estàtica. Els efectes no quasistàtics es capturen mitjançant diferents mètodes, com ara l'enfocament de segmentació de canals o funcions d'escalat depenents de la freqüència de les àrees del transistor on es calculen les càrregues. El model de les càrregues totals es verifica mitjançant mesures de capacitat d'un TFT orgànic esglaonat i per simulacions numèriques de TFT orgànics en les arquitectures esglaonades i coplanars mitjançant el simulador de dispositiu Sentaurus TCAD. Els models no quasistàtics es verifiquen mitjançant mesures d'admitància depenents de la freqüència d'un transistor esglaonat i per mesures de paràmetres de dispersió de transistors coplanars i esglalonats. El model compacte s'implementa en el llenguatge de descripció de hardware Verilog-A i la simulació d'un amplificador diferencial es compara amb les mesures, amb les quals es mostra un bon acord. El model de soroll es verifica mitjançant mesures de TFT orgànics esglalonats i simulacions TCAD. El model compacte mostra en general una bona concordança i flexibilitat en general pel que fa a l'arquitectura del dispositiu (per exemple, esglaonat o coplanar) i els materials utilitzats.Los transistores orgánicos de capa fina son candidatos prometedores para nuevas aplicaciones electrónicas debido a la posibilidad de fabricar dispositivos electrónicos orgánicos a bajas temperaturas en sustratos flexibles como plástico o papel. Esta tesis doctoral trata del desarrollo de un modelo compacto basado en la carga para la descripción del comportamiento capacitivo y el ruido de baja frecuencia en transistores orgánicos de capa fina. A partir de un modelo DC existente, se desarrollan expresiones para las cargas totales en condiciones de operación cuasiestáticas. Los efectos no cuasiestáticos se capturan mediante diferentes métodos, como la aproximación de segmentación del canal o las funciones de escalado dependientes de la frecuencia de las áreas del transistor donde se calculan las cargas. El modelo para las cargas totales se verifica mediante medidas de capacitancia de un TFT orgánico escalonado y mediante simulaciones numéricas de TFT orgánicos en las arquitecturas escalonada y coplanar utilizando el simulador de dispositivo TCAD Sentaurus. Los modelos no cuasiestáticos se verifican mediante medidas de admitancia dependientes de la frecuencia de un transistor escalonado y mediante medidas de parámetros de dispersión de transistores coplanares y escalonados. El modelo compacto se implementó en el lenguaje de descripción de hardware Verilog-A y la simulación de un amplificador diferencial se compara con medidas, observándose una buena concordancia. El modelo de ruido se verifica mediante medidas de TFT orgánicos escalonados y mediante simulaciones TCAD. El modelo compacto muestra en general una buena concordancia y flexibilidad con respecto a la arquitectura del dispositivo (p. ej. escalonado o coplanar) y los materiales utilizados.Organic thin-film transistors are promising candidates for novel electronics applications due to the possibility of fabricating organic electronic devices at low temperatures on flexible substrates like plastic or paper. This doctoral thesis deals with the development of a charge-based compact model for the description of the capacitive behavior and the low-frequency noise in organic thin-film transistors. Based on an existing DC model, expressions for the total charges under quasistatic operation conditions are derived. Non-quasistatic effects are captured by different methods, such as the channel-segmentation approach or frequency-dependent scaling functions of the areas in the transistor where charges are calculated. The model for the total charges is verified by capacitance measurements of a staggered organic TFT and by numerical simulations of organic TFTs in the staggered and coplanar architectures using the device simulator Sentaurus TCAD. The non-quasistatic models are verified by frequency-dependent admittance measurements of a staggered transistor and by scattering-parameter measurements of coplanar and staggered transistors. The compact model is implemented in the hardware description language Verilog-A and the simulation of a differential amplifier is compared to measurements, which shows a good agreement. The noise model is verified by measurements of staggered organic TFTs and by TCAD simulations. The compact model shows an overall good agreement and flexibility with respect to the device architecture (e. g. staggered or coplanar) and the used materials

Analysis of the Deep Sub-Micron a-Si:H Thin Film Transistors

The recent developments of high resolution flat panel imagers have prompted interests in fabricating smaller on-pixel transistors to obtain higher fill factor and faster speed. This thesis presents fabrication and modeling of short channel amorphous silicon (a-Si:H) vertical thin film transistors (VTFT). A variety of a-Si:H VTFTs with different channel lengths, from 100 nm to 1 μm, are successfully fabricated using the discussed processing steps. Different structural and electrical characteristics of the fabricated device are measured. The results of I-V and C-V characteristics are comprehensively discussed. The 100 nm channel length transistor performance is diverged from regular long channel TFT characteristics, as the short channel effects become dominant in the device, giving rise to necessity of having a physical model to explain such effects. An above threshold model for a-Si:H VTFT current characteristics is extracted. The transport mechanisms are explained and simulated for amorphous silicon material to be used in the device model. The final model shows good agreement with experimental results. However, we used numerical simulation, run in Medici, to further verify the model validity. Simulation allows us to vary different device and material parameters in order to optimize fabrication process for VTFT. The capacitance behavior of the device is extensively studied alongside with a TFT breakdown discussion

Organic thin-film transistors:from technologies to circuits

Organic molecules (i.e. carbon-based) have opened a new and rapidly-growing industrial field in the optoelectronic market bringing to this field a new dimension of thinness and flexibility. In this context, this thesis has focused on one particular building block of the vast and emerging field of organic electronics: the organic thin-film transistor (OTFT) which uses organic compounds as semiconductor. Whereas the OTFT-based circuits are not meant to compete with the silicon-based high-end industry (micro-processors...), their performance have already reached levels enabling their use in potential applications such as displays (e-paper, LCD, OLED) or radiofrequency identification (RFID) tags. The continuously growing number of available organic molecules exhibiting conductive, semi-conductive or insulating properties combined with the number of available deposition/patterning methods (e.g. gravure printing) gives more flexibility to the technology. These additional degrees of freedom raise two main questions: How to identify the most suitable OTFT platform for a given application and how to estimate its potential, as for instance in, of digital circuits? This thesis targets to answer to those questions. For this purpose, several OTFT platforms have been screened and their performance have been discussed and compared through standard figures of merit. The self-aligned nano-imprinted technology has demonstrated state-of-the-art sub-micrometer OTFTs on 4-inch flexible substrates. This made this platform the most suitable candidate for developing the potential evaluation framework. For that purpose, a static model suitable for the sub-micrometer OTFTs has been developed which embeds almost all known electrical aspects of OTFTs. Then the device-to-device discrepancy often observed in OTFTs has been studied and statistical modeling methods introduced. This allowed the simulation of sub-micrometer inverters performed with commercially available tools. Next, a statistical method has been developed to evaluate the potential of the sub-micrometer OTFTs for digital applications. Whereas the method concludes that these sub-micrometer OTFTs are not mature enough to make complex digital circuits, this methodology is technology-independent and may thus serve as a basis to characterize unipolar-logic printed electronics and be further extended to complementary-logic circuits. Last but not least, an automation effort has been undergone all along this thesis in order to increase the throughput for such demanding data analysis. The main outcome of this task is a user-friendly multi-analysis and parameter extraction platform

Interpretation and Physical Modeling of Electronic Transport and Defect States in IGZO Thin-Film Transistors

This work is a comprehensive study on the interpretation and modeling of electronic transport behavior and defect states in indium-gallium-zinc-oxide (IGZO) TFTs. Key studies have focused on advancing the state of IGZO TFTs by addressing several challenges in device stability, scaling, and device modeling. These studies have provided new insight on the associated mechanisms and have resulted in the realization of scaled thin-film transistors that exhibit excellent electrical performance and stability. This work has demonstrated the ability to scale the conventional inverted staggered IGZO TFT down to one micron channel length, with excellent on-state and off-state performance where the VT ≈1 V, µeff =12 cm2/Vs, Ileak ≤ 10-12 A/µm and SS ≈ 160 mV/dec. The working source/drain electrodes are direct metal contact regions to the IGZO, which requires several microns of gate overlap to provide ohmic behavior with minimal series resistance and ensure tolerance to overlay error. New results utilizing ion implantation for self-aligned source/drain regions present a path towards submicron channel length. This strategy offers a reduction in channel length as well as parasitic capacitance, which translates to improvement in RC delay and associated voltage losses due to charge-sharing. The realization of self-aligned TFTs using boron ion implantation for selective activation was introduced in a first-time report of boron-doped IGZO. Cryogenic measurements made on long-channel devices has revealed temperature-dependent behavior that is not explained by existing TCAD models employed for defect states and carrier mobility. A completely new device model using Silvaco Atlas has been established which properly accounts for the role of donor-like oxygen vacancy defects, acceptor-like band-tail states, acceptor-like interface traps, and a temperature-dependent intrinsic channel mobility. The developed model demonstrates a remarkable match to transfer characteristics measured at T = 150 K to room temperature. A power-law fit for the µch = f(T) relationship, which resembles 〖μ ~ T〗^((+3)⁄2) behavior consistent with ionized defect scattering. The mobility model is expressly independent of carrier concentration, without dependence on the applied gate bias. The device model is consistent with a compact model developed for circuit simulation (SPICE) that has been recently refined to include on-state and off-state operation. While IGZO is the only AOS technology mature enough for commercialization, the effective electron channel mobility µeff ~ 10 cm2/Vs presents a performance limitation. Other candidate AOS materials which have higher reported channel mobility values have also been investigated; specifically, indium-tungsten-oxide (IWO) and indium-gallium-tin-oxide (ITGO). These investigations serve as preliminary studies; device characteristics support the claims of high channel mobility; however the influence of defect states clearly indicates the need for further process development. The advancements realized in IGZO TFTs in this work will serve as a foundation for these alternative AOS materials

Towards development of flexible sensor systems based on organic thin-film transistors

To date, significant progress has been made to advance the performance of organic thin film transistors (OTFTs). These included new materials and structures and innovative fabrication methods to yield properties such as light-weight, mechanical flexibility, and low temperature fabrication. Yet, many OTFTs still suffer from low on-state drain current and electrical instability seen as a hysteresis or a shift in the transistor transfer characteristics, thus hindering wider OTFT applications. This thesis aims to tackle these issues by presenting low-voltage OTFTs based on air-stable dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) and hydrophobic bi-layer dielectric made of aluminium oxide and octadecyl phosphonic acid (AlOx/C18PA) on PEN substrates. The fabricated transistors are approximately hysteresis-free and exhibit on-state drain current approaching 100 μA at gate-source and drain-source voltages of –2 V. This is a notable advancement compared to the performance of similar devices reported in the literature and indicative of a robust design and fabrication. High on-state drain current was enabled by ultra-thin gate dielectric and interdigitated source/drain contacts leading to high channel width-to-length ratio and small transistor area. The electrical stability was studied in the above transistors, both fresh and aged. AC square pulses with constant bias time of 1 second and varying pulse period were simultaneously applied to gate and drain of the transistor to simulate the recurrent turn-on/turn-off transistor operation. OTFT performance marginally degraded under AC pulses, with the exception of field-effect mobility that improved. Degradation proceeded faster in aged OTFTs stored in dark ambient environment but the on-state drain current stabilised after ~500 pulses. The stabilisation resulted from the rising field-effect mobility compensating the threshold voltage increase. Finally, the inclusion of the above OTFT as a voltage amplifier in a temperature sensor system raised the temperature sensitivity by a factor of ~5, thus laying foundation for future flexible sensors and circuit applications.To date, significant progress has been made to advance the performance of organic thin film transistors (OTFTs). These included new materials and structures and innovative fabrication methods to yield properties such as light-weight, mechanical flexibility, and low temperature fabrication. Yet, many OTFTs still suffer from low on-state drain current and electrical instability seen as a hysteresis or a shift in the transistor transfer characteristics, thus hindering wider OTFT applications. This thesis aims to tackle these issues by presenting low-voltage OTFTs based on air-stable dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) and hydrophobic bi-layer dielectric made of aluminium oxide and octadecyl phosphonic acid (AlOx/C18PA) on PEN substrates. The fabricated transistors are approximately hysteresis-free and exhibit on-state drain current approaching 100 μA at gate-source and drain-source voltages of –2 V. This is a notable advancement compared to the performance of similar devices reported in the literature and indicative of a robust design and fabrication. High on-state drain current was enabled by ultra-thin gate dielectric and interdigitated source/drain contacts leading to high channel width-to-length ratio and small transistor area. The electrical stability was studied in the above transistors, both fresh and aged. AC square pulses with constant bias time of 1 second and varying pulse period were simultaneously applied to gate and drain of the transistor to simulate the recurrent turn-on/turn-off transistor operation. OTFT performance marginally degraded under AC pulses, with the exception of field-effect mobility that improved. Degradation proceeded faster in aged OTFTs stored in dark ambient environment but the on-state drain current stabilised after ~500 pulses. The stabilisation resulted from the rising field-effect mobility compensating the threshold voltage increase. Finally, the inclusion of the above OTFT as a voltage amplifier in a temperature sensor system raised the temperature sensitivity by a factor of ~5, thus laying foundation for future flexible sensors and circuit applications

High-performance Zinc Oxide Thin-Film Transistors For Large Area Electronics

The increasing demand for high performance electronics that can be fabricated onto large area substrates employing low manufacturing cost techniques in recent years has fuelled the development of novel semiconductor materials such as organics and metal oxides, with tailored physical characteristics that are absent in their traditional inorganic counterparts such as silicon. Metal oxide semiconductors, in particular, are highly attractive for implementation into thin-film transistors because of their high charge carrier mobility, optical transparency, excellent chemical stability, mechanical stress tolerance and processing versatility. This thesis focuses on the development of high performance transistors based on zinc oxide (ZnO) semiconducting films grown by spray pyrolysis (SP), a low cost and highly scalable method that has never been used before for the manufacturing of oxide-based thin-film transistors. The physical properties of as-grown ZnO films have been studied using a range of techniques. Despite the simplicity of SP, as-fabricated transistors exhibit electrical characteristics comparable to those obtained from ZnO devices produced using highly sophisticated deposition processes. In particular, electron mobility up to 25 cm2/Vs has been achieved in transistors based on pristine ZnO films grown at 400 °C onto Si/SiO2 substrates utilising aluminium source-drain (S-D) electrodes. A strong dependence of the saturation mobility on the work function of S-D electrodes and the transistor channel length (L) has been established. Short channel transistors are found to exhibit improved performance as compared to long channel ones. This was attributed to grain boundary effects that tend to dominate charge transport in devices with L < 40 μm. High mobility, low operating voltage (<1.5 V) ZnO transistors have also been developed and characterised. This was achieved through the combination of SP, for the deposition of ZnO, and thermally stable solution-processed self-assembling monolayer gate dielectrics. Detailed study of the temperature dependence of the operating characteristics of ZnO transistors revealed a thermally activated electron transport process that was described by invoking the multiple trapping and release model. Importantly, ZnO transistors fabricated by SP are found to exhibit highly stable operating characteristics with a shelf lifetime of several months. The simple SPbased fabrication paradigm demonstrated in this thesis expands the possibilities for the development of advanced simple as well as multi-component oxide semiconductors far beyond those accessible by traditional deposition methods such as sputtering. Furthermore, it offers unprecedented processing scalability hence making it attractive for the manufacturing of future ubiquitous oxide electronics

Exploring polymer dielectrics for donor-acceptor and small molecule based transistors and voltage inverters

Organic semiconductor devices have gained much attention over the past several decades. Solution processability of polymer materials lends itself towards the realization of flexible, wearable electronic devices, owing to the low energy needs and the applicability of large-scale roll-to-roll casting methods. Unlike traditional field effect transistor technologies which rely on doped semiconductors and operate in the inversion regime, organic transistor devices utilize intrinsic semiconductors and operate in the accumulation regime. For this reason, the unique physical properties of both the dielectric layer and the semiconductor layer are crucial to driving charge transport. Hole-transporting field effect transistors were fabricated using the ferroelectric polymer poly(vinylidene fluoride-trifluoroethylene) as the dielectric along with a donor-acceptor polymer based on diketopyrrolopyrrole as the semiconductor layer. These devices yield carrier mobilities upwards of 0.4 cm2/Vs and high on/off ratios when the ferroelectric layer is electrically poled. Furthermore, through the application of self-assembled monolayers, the device characteristics are observed to be modified by orders of magnitude for devices of the same architecture utilizing a non-ferroelectric dielectric. Fluorination of donor-acceptor copolymers has been one strategy employed towards enhancing polymer coplanarity, increasing crystallinity, and improving charge transport mechanisms in organic devices. Towards the realization of dedicated n-type polymer semiconductors, the synthesis of thiazole flanked fluorinated isoindigo copolymers is reported and their field effect transistor properties are demonstrated. The selenophene-substituted isoindigo shows improved performance over the thiophene units. Top-gate devices with varying dielectric layers showed n-type transport with electron carrier mobilities of the order of 10-2 cm2/Vs and on/off ratio of 105. Several proof-of-concept complementary voltage inverter circuits have been constructed utilizing the various dielectrics and donor-acceptor semiconductors explored prior in this work. In addition to these, ozone-treated zinc oxide and the donor-acceptor polymer quinoxaline are explored for application in constructing inverter circuits. The contribution of each device's characteristic to the overall inverter behavior is demonstrated. Furthermore, a basic inverter model is used to simulate the inverter characteristics of one such circuit using parameters from the individual device characteristics. A viable route for enhancing the dielectric constant of polymer dielectrics is via the incorporation of semiconducting and insulating nanoparticles. Returning the focus back to the influence of the dielectric layer, improved performance of organic capacitor and transistor devices after incorporating magnetic nanoparticles into non-ferroelectric dielectrics is observed. In particular, the threshold voltage, subthreshold swing, and observable hysteresis are reduced in pentacene devices using cross-linked poly(4-vinyl phenol) polymer dielectric with incorporated cobalt ferrite nanoparticles. The application of an external magnetic field is also observed to further tune device behavior.Includes bibliographical references