Modeling Of Two Dimensional Graphene And Non-graphene Material Based Tunnel Field Effect Transistors For Integrated Circuit Design

The Moore’s law of scaling of metal oxide semiconductor field effect transistor (MOSFET) had been a driving force toward the unprecedented advancement in development of integrated circuit over the last five decades. As the technology scales down to 7 nm node and below following the Moore’s law, conventional MOSFETs are becoming more vulnerable to extremely high off-state leakage current exhibiting a tremendous amount of standby power dissipation. Moreover, the fundamental physical limit of MOSFET of 60 mV/decade subthreshold slope exacerbates the situation further requiring current transport mechanism other than drift and diffusion for the operation of transistors. One way to limit such unrestrained amount of power dissipation is to explore novel materials with superior thermal and electrical properties compared to traditional bulk materials. On the other hand, energy efficient steep subthreshold slope devices are the other possible alternatives to conventional MOSFET based on emerging novel materials. This dissertation addresses the potential of both advanced materials and devices for development of next generation energy efficient integrated circuits. Among the different steep subthreshold slope devices, tunnel field effect transistor (TFET) has been considered as a promising candidate after MOSFET. A superior gate control on source-channel band-to-band tunneling providing subthreshold slopes well below than 60 mV/decade. With the emergence of atomically thin two-dimensional (2D) materials, interest in the design of TFET based on such novel 2D materials has also grown significantly. Graphene being the first and the most studied among 2D materials with exotic electronic and thermal properties. This dissertation primarily considers current transport modeling of graphene based tunnel devices from transport phenomena to energy efficient integrated circuit design. Three current transport models: semi-classical, semi-quantum and numerical simulations are described for the modeling of graphene nanoribbon tunnel field effect transistor (GNR TFET) where the semi-classical model is in close agreement with the quantum transport simulation. Moreover, the models produced are also extended for integrated circuit design using Verilog-A hardware description language for logic design. In order to overcome the challenges associated with the band gap engineering for making graphene transistor for logic operation, the promise of graphene based interlayer tunneling transistors are discussed along with their existing fundamental physical limitation of subthreshold slope. It has been found that such interlayer tunnel transistor has very poor electrostatic gate control on drain current. It gives subthreshold slope greater than the thermionic limit of 60 mV/decade at room temperature. In order to resolve such limitation of interlayer tunneling transistors, a new type of transistor named “junctionless tunnel effect transistor (JTET)” has been invented and modeled for the first time considering graphene-boron nitride (BN)-graphene and molybdenum disulfide (MoS2)-boron nitride (BN) heterostructures, where the interlayer tunneling mechanism controls the source-drain ballistic transport instead of depleting carriers in the channel. Steep subthreshold slope, low power and high frequency THz operation are few of the promising features studied for such graphene and MoS2 JTETs. From current transport modeling to energy efficient integrated circuit design using Verilog-A has been carried out for these new devices as well. Thus, findings in this dissertation would suggest the exciting opportunity of a new class of next generation energy efficient material based transistors as switches

Imperfection-Aware Design of CNFET Digital VLSI Circuits

Carbon nanotube field-effect transistor (CNFET) is one of the promising candidates as extensions to silicon CMOS devices. The CNFET, which is a 1-D structure with a near-ballistic transport capability, can potentially offer excellent device characteristics and order-of-magnitude better energy-delay product over standard CMOS devices. Significant challenges in CNT synthesis prevent CNFETs today from achieving such ideal benefits. CNT density variation and metallic CNTs are the dominant type of CNT variations/imperfections that cause performance variation, large static power consumption, and yield degradation. We present an imperfection-aware design technique for CNFET digital VLSI circuits by: 1) Analytical models that are developed to analyze and quantify the effects of CNT density variation on device characteristics, gate and system levels delays. The analytical models, which were validated by comparison to real experimental/simulation data, enables us to examine the space of CNFET combinational, sequential and memory cells circuits to minimize delay variations. Using these model, we drive CNFET processing and circuit design guidelines to manage/overcome CNT density variation. 2) Analytical models that are developed to analyze the effects of metallic CNTs on device characteristics, gate and system levels delay and power consumption. Using our presented analytical models, which are again validated by comparison with simulation data, it is shown that the static power dissipation is a more critical issue than the delay and the dynamic power of CNFET circuits in the presence of m-CNTs. 3) CNT density variation and metallic CNTs can result in functional failure of CNFET circuits. The complete and compact model for CNFET probability of failure that consider CNT density variation and m-CNTs is presented. This analytical model is applied to analyze the logical functional failures. The presented model is extended to predict opportunities and limitations of CNFET technology at todays Gigascale integration and beyond.\u2

Large-signal model of 2DFETs: compact modeling of terminal charges and intrinsic capacitances

We present a physics-based circuit-compatible model for double-gated two-dimensional semiconductor based field effect transistors, which provides explicit expressions for the drain current, terminal charges and intrinsic capacitances. The drain current model is based on the drift-diffusion mechanism for the carrier transport and considers Fermi-Dirac statistics coupled with an appropriate field-effect approach. The terminal charge and intrinsic capacitance models are calculated adopting a Ward-Dutton linear charge partition scheme that guarantees charge-conservation. It has been implemented in Verilog-A to make it compatible with standard circuit simulators. In order to benchmark the proposed modeling framework we also present experimental DC and high-frequency measurements of a purposely fabricated monolayer MoS2 FET showing excellent agreement between the model and the experiment and thus demonstrating the capabilities of the combined approach to predict the performance of 2DFETs.Comment: 7 pages, 6 figure

Integrated Circuits/Microchips

With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

Magnetic Graphene Memory Circuit Characterization And Verilog-A Modeling

Memory design plays an important role in modern computer technology in regard to overall performance and reliability. Prior memory technologies, including magneticcore memory, hard disk drives, DRAM, SRAM have limitations in regard to bit density, IC integration, power efficiency, and physical size, respectively. To address these limitations we propose to develop a magnetic graphene random access memory (MGRAM) utilizing graphene Hall effect, which takes advantage of the inherent reliability of magnetic memory and superior electrical properties of graphene (high carrier mobility, zero-band gap, high Hall sensitivity). As the graphene magnetic memory device will be integrated with a CMOS ASIC design an analog circuit model for the MGRAM cell is necessary and important. In this study the electrical circuit model is developed utilizing the analog circuit modeling language Verilog-A. The electrical circuit model characterizes the graphene electrical properties and the ferromagnetic core magnetic properties that retains the bit-state value. MGRAM device simulations studying varying coil width, height, radius, contact pad configuration, graphene shape, is performed with the MagOasis Magsimus tool to evaluate the device performance. Model results show a maximum Hall effect voltage of 100mV for a bias current of 50uA with a 1 Tesla magnetic field, and a writing speed of 6-9ns for setting the magnetic state. These results will be validated against the circuit hardware measurement and will be used for model refinement

Recent Advances in Ambipolar Transistors for Functional Applications

Ambipolar transistors represent a class of transistors where positive (holes) and negative (electrons) charge carriers both can transport concurrently within the semiconducting channel. The basic switching states of ambipolar transistors are comprised of common offâ state and separated onâ state mainly impelled by holes or electrons. During the past years, diverse materials are synthesized and utilized for implementing ambipolar charge transport and their further emerging applications comprising ambipolar memory, synaptic, logic, and lightâ emitting transistors on account of their special bidirectional carrierâ transporting characteristic. Within this review, recent developments of ambipolar transistor field involving fundamental principles, interface modifications, selected semiconducting material systems, device structures, ambipolar characteristics, and promising applications are highlighted. The existed challenges and prospective for researching ambipolar transistors in electronics and optoelectronics are also discussed. It is expected that the review and outlook are well timed and instrumental for the rapid progress of academic sector of ambipolar transistors in lighting, display, memory, as well as neuromorphic computing for artificial intelligence.Ambipolar transistors represent transistors that allow synchronous transport of electrons and holes and their accumulation within semiconductors. This review provides a comprehensive summary of recent advances in various semiconducting materials realized in ambipolar transistors and their functional memory, synapse, logic, as well as lightâ emitting applications.Peer Reviewedhttps://deepblue.lib.umich.edu/bitstream/2027.42/151885/1/adfm201902105_am.pdfhttps://deepblue.lib.umich.edu/bitstream/2027.42/151885/2/adfm201902105.pd

정전기수력학 인쇄를 활용한 단일벽 탄소나노튜브 기반 트랜지스터 및 응용

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·컴퓨터공학부, 2020. 8. 홍용택.As the demand and research for electronic devices on flexible and stretchable substrates gradually continues comparable to the conventional rigid silicon-based electronic devices, interest in new semiconducting materials capable of low-temperature processes and large-area processes is increasing. Single-walled carbon nanotube (SWCNT) is one of the representative materials satisfying the new interests thanks to its excellent electrical and mechanical properties. SWCNT can be advantageous for non-vacuum, low-temperature, and large-area processes in response to various solution processes such as dipping, inkjet printing, and gravure printing. For high-performance devices with low power consumption based on next-generation electronics, the demand for ultra-fine patterning technology based on the solution process is also increasing. In this thesis, SWCNT-based all electrohydrodynamic-jet (E-jet) printing system was established, a SWCNT-based thin-film transistor (SWCNT-TFT) with a channel length of 5 microns was implemented through the system. In addition, by developing and grafting technology to control the threshold voltage of SWCNT-TFTs based on the solution process, we have demonstrated highly integrated and high-resolution SWCNT-based applications including logic gate, pixel circuits for image detector and display. In addition to the micrometer scale fine pattern technology by the E-jet printing system, a new solution process-based vertical stacking technology is also introduced to further improve the transistor density, enabling high-resolution, highly integrated electronic applications in a continuous environment without any vacuum or high temperature process. The technology introduced in this thesis for high performance, high resolution, and high integration of SWCNT-based devices makes it possible to fabricate a 250 pixel per inch active matrix backplane utilizing only the solution process.유연 기판 및 신축성 기판상의 전자 소자에 대한 수요 및 연구가 종래의 단단한 실리콘 기반의 전자 기술만큼이나 많은 관심을 받고 있어, 이를 위한 저온 공정 및 대면적 공정이 가능한 새로운 반도체 물질 연구에 대한 관심이 증가하고 있다. 단일벽 탄소나노튜브는 뛰어난 전기적 및 기계적 특성 뿐만 아니라 비 진공, 저온, 그리고 대면적 공정이 가능한 담금 공정, 잉크젯 프린팅, 그리고 그라비아 인쇄법과 같은 용액공정에 대응하기에 이러한 요구를 충분히 충족시킨다. 마찬가지로 용액 공정 기반 소자의 고성능 및 저전력화를 위한 용액 공정기반의 초 미세 패터닝 기술에 대한 필요성도 증가하고 있다. 본 학위 논문에서는 단일벽 탄소나노튜브 기반의 전 정전기수력학 인쇄 시스템을 구축하여 5마이크론의 채널 길이를 갖는 단일벽 탄소나노튜브 기반 박막트랜지스터를 구현하였다. 또한 용액 공정기반의 단일벽 탄소나노튜브 기반 박막트랜지스터의 문턱 전압을 조절하는 기술을 개발하고 이를 접목시켜 논리소자와 영상센서 및 디스플레이를 위한 픽셀 회로를 포함한 단일벽 탄소나노튜브 기반의 고해상도, 고집적화된 응용소자를 개발하였다. 정전기수력학 인쇄 시스템을 통한 마이크론 수준의 미세 패터닝 기술 뿐만 아니라 집적도를 더욱 향상시키기 위한 용액 공정기반의 새로운 수직 적층형 기술을 도입하여 고해상도 및 고집적화된 단일벽 탄소나노튜브 기반의 전자 소자를 어떠한 진공 공정이나 고온공정 없이 연속된 환경에서 구현하였다. 본 학위논문에서 제시한 단일벽 탄소나노튜브 기반 소자의 고성능, 고해상도, 고집적화를 위한 기술은 250 ppi급의 능동형 매트릭스 백플레인의 제작을 순수 용액공정만으로 실현 가능하게 한다.1 Introduction 1 1.1 Single-Walled Carbon Nanotubes 1 1.2 Band structure of SWCNTs 8 1.2.1 Energy bandgap of SWCNTs 8 1.2.2 Density of states for SWCNTs 11 1.2.3 Detection for classifying species of SWCNTs 13 1.3 Sorting out semiconducting SWCNTs 16 1.3.1 Pre-deposition of the nanotubes and sorting later 16 1.3.2 First sorting out SWCNTs and deposition later 18 1.4 Operation of SWCNT-TFTs 21 1.4.1 SWCNT-TFTs as Schottky-barrier FETs 22 1.4.2 Random network of SWCNTs 26 1.5 Reported SWCNT-TFTs and applications 28 1.6 Technical points for microelectronics based on SWCNT-TFTs 32 1.7 Organization 34 2 Tunable threshold voltage in single-walled carbon nanotube thin-film transistors 35 2.1 Introduction 35 2.2 Experimental details 37 2.2.1 Fabrication process for solution-processed SWCNT-TFTs 37 2.2.2 Post-treatments for tunable threshold voltage in solution-processed SWCNT-TFTs and measurement of their electrical properties 38 2.3 Results and discussion 39 2.3.1 Post-chemical encapsulation for tunable threshold voltage 39 2.3.2 Contact resistance analysis by the Y-function method in SWCNT-TFTs employing chemical encapsulation 41 2.3.3 Shift of energy band in SWCNT-TFTs 42 2.3.4 Cycling tests for post-treatments 45 2.3.5 SWCNTs-based p-type only inverter 46 2.4 Conclusion 49 3 All electrohydrodynamic-jet printing system for single-walled carbon nanotube thin-film transistors 50 3.1 Introduction 50 3.2 Experimental details 55 3.2.1 Ink manufacturing for E-jet printed metal, dielectric, and active layers 55 3.2.2 Optimized E-jet printing conditions and fabrication process for all E-jet printed SWCNT-TFTs 57 3.3 Results and discussion 60 3.3.1 Constituting of all E-jet printing system 60 3.3.2 Optimized E-jet printed metal electrode 63 3.3.3 Optimized E-jet printed polymer dielectric 67 3.3.4 E-jet printing of S/D electrodes with short channel length 74 3.3.5 Formation of SWCNT networks in E-jet printing system 76 3.3.6 Overall process for all E-jet printing and electrical characteristics of all E-jet printed SWCNT-TFTs 78 3.4 Conclusion 83 4 All electrohydrodynamic-jet printing system based circuit design for high-resolution and highly integrated applications 85 4.1 Introduction 85 4.2 Experimental details 89 4.2.1 In-situ fabrication of via-hole and diode-connected SWCNTs-TFTs in all E-jet printing system 89 4.2.2 Fabrication process of all E-jet printed inverter with vertically stacked SWCNT-TFTs 90 4.2.3 Fabrication process of all E-jet printed active pixel sensor for image sensor with vertical stacking structure 92 4.2.4 Fabrication process of all E-jet printed pixel circuit for active matrix polymer light-emitting diode with vertical stacking structure 95 4.3 Results and discussion 98 4.3.1 In-situ via-hole formation technology based on all E-jet printing system 98 4.3.2 Additional E-jet printing of PVP layer on the SWCNT-TFTs 99 4.3.3 Electrical characteristics for all E-jet printed diode-connected SWCNT-TFTs 101 4.3.4 Electrical characteristics for all E-jet printed inverter with vertically stacked SWCNT-TFTs 103 4.3.5 Structure design for active pixel sensor based on vertically stacked E-jet printed SWCNT-TFTs 107 4.3.6 All E-jet printed pixel circuit for active matrix polymer light-emitting diode with vertical stacking structure 110 4.4 Conclusion 118 5 Conclusion 119 Appendix 121 A.1 Post-treatment with DI-water on SWCNT-TFT 121 A.2 Variation of characteristics of SWCNT-TFTs by post-treatment time with NH4OH 123 A.3 Surface energy variation by a ratio between cross-liking agent and PVP 124 A.4 Analysis for surface roughness parameters 125 A.5 Electrical characteristics of E-jet printed SWCNT-TFTs according to channel structure 128 Bibliography 130 Abstract in Korean 149Docto

Field-effect based chemical and biological sensing : theory and implementation

Electrochemical sensors share many properties of an ideal (bio)chemical sensor. They can be easily miniaturized with high parallel sensing capabilities,with rugged structure and at low cost. The response obtained from thetarget analyte is directly in electrical form allowing convenient data post-processing and simple interfacing to standard electrical components. With field-effect transistor (FET) based sensors, the transducing principle relies on direct detection of interfacial charge allowing detection of various ions and charged macromolecules. This thesis investigates FET based sensors for biological and chemical sensing. First, an ion-sensitive floating gate FET (ISFGFET) structure is studied and modeled. The proposed model reveals novel abilities of the structure not found in conventional ion-sensitive FETs (ISFETs). With IS-FGFET, we can simultaneously optimize the transistor operating point and modulate the charging of the surface and the ionic screening layer via the field effect. This control is predicted to allow reduced electric double layer screening as well as the possibility to enhance charged molecule attachment to the sensing surface. The model can predict sensor characteristic curves in pH sensing in absolute terms and allows any potential to be computed in the sensor including the electrical part and the electrolyte solution. Furthermore, a compact ISFGFET variant is merged into electric circuit simulator, which allows it to be simulated as a standard electrical component with electrical simulations tools of high computational efficiency, and allows simple modifications such as addition of parasitic elements, temperature effects, or even temporal drifts. Next, another transistor based configuration, the extended-gate ISFET is studied. The simplicity of the proposed configuration allows a universal potentiometric approach where a wide variety of chemical and biological sensors can be constructed. The design philosophy for this sensing structure is to use the shelf electric components and standard electric manufacturing processes. Such an extended-gate structure is beneficial since the dry electronics can be completely separated from the wet sensing environment. The extended-gate allows simple functionalization towards chemical and biological sensing. A proof-of-concept of this structure was verified through organo modified gold platforms with ion-selective membranes. A comparison with standard open-circuit potentiometry reveals that the sensing elements in a disposable sensing platform arrays provide comparable performance to traditional electrodes. Finally, a universal battery operated hand-held electrical readout device is designed for multiplexed detection of the disposable sensors with wireless smartphone data plotting, control, and storage. Organic polymers play an important role in the interfacial properties of sensors studied in this thesis. The polymer coating is attractive in chemical sensing because of its redox sensitivity, bio-immobilization capability, ion-to-electron transducing capability, and applicability, for example via a simple low-cost drop-casting. This structure simplifies the design of the sensor substantially and the coating increases the amount of possible target applications.Siirretty Doriast