323 research outputs found
Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design
This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis.
First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise.
The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling.
In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast
Modelling and analysis of crosstalk in scaled CMOS interconnects
The development of a general coupled RLC interconnect model for simulating scaled bus structures m VLSI is presented. Several different methods for extracting submicron resistance, inductance and capacitance parameters are documented. Realistic scaling dimensions for deep submicron design rules are derived and used within the model. Deep submicron HSPICE device models are derived through the use of constant-voltage scaling theory on existing 0.75µm and 1.0µm models to create accurate interconnect bus drivers. This complete model is then used to analyse crosstalk noise and delay effects on multiple scaling levels to determine the dependence of crosstalk on scaling level. Using this data, layout techniques and processing methods are suggested to reduce crosstalk in system
Design and modelling of variability tolerant on-chip communication structures for future high performance system on chip designs
The incessant technology scaling has enabled the integration of functionally complex System-on-Chip (SoC) designs with a large number of heterogeneous systems on a single chip. The processing elements on these chips are integrated through on-chip communication structures which provide the infrastructure necessary for the exchange of data and control signals, while meeting the strenuous physical and design constraints. The use of vast amounts of on chip communications will be central to future designs where variability is an inherent characteristic. For this reason, in this thesis we investigate the performance and variability tolerance of typical on-chip communication structures. Understanding of the relationship between variability and communication is paramount for the designers; i.e. to devise new methods and techniques for designing performance and power efficient communication circuits in the forefront of challenges presented by deep sub-micron (DSM) technologies.
The initial part of this work investigates the impact of device variability due to Random Dopant Fluctuations (RDF) on the timing characteristics of basic communication elements. The characterization data so obtained can be used to estimate the performance and failure probability of simple links through the methodology proposed in this work. For the Statistical Static Timing Analysis (SSTA) of larger circuits, a method for accurate estimation of the probability density functions of different circuit parameters is proposed. Moreover, its significance on pipelined circuits is highlighted. Power and area are one of the most important design metrics for any integrated circuit (IC) design. This thesis emphasises the consideration of communication reliability while optimizing for power and area. A methodology has been proposed for the simultaneous optimization of performance, area, power and delay variability for a repeater inserted interconnect. Similarly for multi-bit parallel links, bandwidth driven optimizations have also been performed. Power and area efficient semi-serial links, less vulnerable to delay variations than the corresponding fully parallel links are introduced. Furthermore, due to technology scaling, the coupling noise between the link lines has become an important issue. With ever decreasing supply voltages, and the corresponding reduction in noise margins, severe challenges are introduced for performing timing verification in the presence of variability. For this reason an accurate model for crosstalk noise in an interconnection as a function of time and skew is introduced in this work. This model can be used for the identification of skew condition that gives maximum delay noise, and also for efficient design verification
Investigation of Interconnect and Device Designs for Emerging Post-MOSFET and Beyond Silicon Technologies
Title from PDF of title page viewed May 31, 2017Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 94-108)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2016The integrated circuit industry has been pursuing Moore’s curve down to deep
nanoscale dimensions that would lead to the anticipated delivery of 100 billion transistors on
a 300 mm² die operating below 1V supply in the next 5-10 years. However, the grand challenge
is to reliably and efficiently take the full advantage of the unprecedented computing power
offered by the billions of nanoscale transistors on a single chip. To mitigate this challenge, the
limitations of both the interconnecting wires and semiconductor devices in integrated circuits
have to be addressed.
At the interconnect level, the major challenge in current high density integrated circuit
is the electromagnetic and electrostatic impacts in the signal carrying lines. Addressing these
problems require better analysis of interconnect resistance, inductance, and capacitance.
Therefore, this dissertation has proposed a new delay model and analyzed the time-domain
output response of complex poles, real poles, and double poles for resistance-inductance
capacitance interconnect network based on a second order approximate transfer function. Both
analytical models and simulation results show that the real poles model is much faster than the
complex poles model, and achieves significantly higher accuracy in order to characterize the
overshoot and undershoot of the output responses.
On the other hand, the semiconductor industry is anticipating that within a decade
silicon devices will be unable to meet the demands at nanoscale due to dimension and material
scaling. Recently, molybdenum disulfide (MoS₂) has emerged as a new super material to
replace silicon in future semiconductor devices. Besides, conventional field effect transistor
technology is also reaching its thermodynamic limit. Breaking this thermal and physical limit
requires adoption of new devices based on tunneling mechanism. Keeping the above
mentioned trends, this dissertation also proposed a multilayer MoS₂ channel-based tunneling
transistor and identifies the fundamental parameters and design specifications that need to be
optimized in order to achieve higher ON-currents. A simple analytical model of the proposed
device is derived by solving the time-independent Schrodinger equation. It is analytically
proven that the proposed device can offer an ON-current of 80 A/m, a subthreshold swing
(S) of 9.12 mV/decade, and a / ratio of 10¹².Introduction -- Previous models on interconnect designs -- Proposed delay model for interconnect design -- Investigation of tunneling for field effect transistor -- Study of molybdenum disulfide for FET applications -- Proposed molybdenum disulfide based tunnel transistor -- Conclusion -- Appendix A. Derivation of time delay model -- Appendix B. Derivation of tunneling current model Appendix C. Derivation of subthreshold swing mode
Exploration and Design of High Performance Variation Tolerant On-Chip Interconnects
Siirretty Doriast
I/O port macromodelling
3D electromagnetic modelling and simulation of various Printed Circuit Board (PCB) components is an important technique for characterizing the Signal Integrity (SI) and Electromagnetic Compatibility (EMC) issues present in a PCB. However, due to limited computational resource and the complexity of the integrated circuits, it is currently not possible to fully model a complete PCB system with 3D electromagnetic solvers. An effort has been made to fully model the PCB with all its components and their S-parameters has been derived so as to integrate these S-parameters in 1D, 2D static or quasi-static field solver or circuit solver tool. The novelty of this thesis is the development and verification of active circuit such as Input and Output buffers and passive channel components such as interconnects, via and connectors and deriving their S-parameters in order to model and characterize the complete PCB using 3D full field solver based on Transmission Line Matrix modelling (TLM) method.
An integration of Input/Output (I/O) port in the 3D full field modelling method allows for modelling of the complete PCB system without being computationally expensive. This thesis presents a method for integration of Input/Output port in the 3D time domain modelling environment. Several software tools are available in the market which can characterize these PCBs in the frequency as well as the time domain using 1D, 2D techniques or using circuit solver such as spice. The work in this thesis looks at extending these 1D and 2D techniques for 3D Electromagnetic solvers in the time domain using the TLM technique for PCB analysis. The modelling technique presented in this thesis is based on in-house developed 3D TLM method along with a developed behavioral Integrated Circuit (IC) – macromodel.
The method has been applied to a wide variety of PCB topologies along with a range of IC packages to fully validate the approach. The method has also been applied to show the switching effect arising out of the crosstalk in a logic device apart from modelling various discontinuities of PCB interconnects in the form of S11 and S21 parameters.
The proposed novel TLM based technique has been selected based on simplification of its approach, electrical equivalence (rather than complex mathematical functions of Maxwell's electromagnetic theory), time domain analysis for transients in a PCB with an increased accuracy over other available methods in the literature. On the experimental side two, four and six layered PCBs with various interconnect discontinuities such as straight line, right angle, fan-out and via and IC packages such as SOT-23 (DBV), SC-70 (DCK) and SOT-553 (DRL) has been designed and manufactured. The modelling results have been verified with the experimental results of these PCBs and other commercial software such as HSPICE, CST design studio available in the market. While characterizing the SI issues, these modelling results can also help in analyzing conducted and radiated EMC/EMI problems to meet various EMC regulations such as CE, FCC around the world
Physical parameter-aware Networks-on-Chip design
PhD ThesisNetworks-on-Chip (NoCs) have been proposed as a scalable, reliable
and power-efficient communication fabric for chip multiprocessors
(CMPs) and multiprocessor systems-on-chip (MPSoCs). NoCs determine
both the performance and the reliability of such systems, with a
significant power demand that is expected to increase due to developments
in both technology and architecture. In terms of architecture, an
important trend in many-core systems architecture is to increase the
number of cores on a chip while reducing their individual complexity.
This trend increases communication power relative to computation
power. Moreover, technology-wise, power-hungry wires are dominating
logic as power consumers as technology scales down. For these
reasons, the design of future very large scale integration (VLSI) systems
is moving from being computation-centric to communication-centric.
On the other hand, chip’s physical parameters integrity, especially
power and thermal integrity, is crucial for reliable VLSI systems. However,
guaranteeing this integrity is becoming increasingly difficult with
the higher scale of integration due to increased power density and operating
frequencies that result in continuously increasing temperature
and voltage drops in the chip. This is a challenge that may prevent
further shrinking of devices. Thus, tackling the challenge of power
and thermal integrity of future many-core systems at only one level
of abstraction, the chip and package design for example, is no longer
sufficient to ensure the integrity of physical parameters. New designtime
and run-time strategies may need to work together at different
levels of abstraction, such as package, application, network, to provide
the required physical parameter integrity for these large systems. This
necessitates strategies that work at the level of the on-chip network
with its rising power budget.
This thesis proposes models, techniques and architectures to improve
power and thermal integrity of Network-on-Chip (NoC)-based
many-core systems. The thesis is composed of two major parts: i)
minimization and modelling of power supply variations to improve
power integrity; and ii) dynamic thermal adaptation to improve thermal
integrity. This thesis makes four major contributions. The first is
a computational model of on-chip power supply variations in NoCs.
The proposed model embeds a power delivery model, an NoC activity
simulator and a power model. The model is verified with SPICE simulation
and employed to analyse power supply variations in synthetic
and real NoC workloads. Novel observations regarding power supply
noise correlation with different traffic patterns and routing algorithms
are found. The second is a new application mapping strategy aiming
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to minimize power supply noise in NoCs. This is achieved by defining
a new metric, switching activity density, and employing a force-based
objective function that results in minimizing switching density. Significant
reductions in power supply noise (PSN) are achieved with a low
energy penalty. This reduction in PSN also results in a better link timing
accuracy. The third contribution is a new dynamic thermal-adaptive
routing strategy to effectively diffuse heat from the NoC-based threedimensional
(3D) CMPs, using a dynamic programming (DP)-based distributed
control architecture. Moreover, a new approach for efficient extension
of two-dimensional (2D) partially-adaptive routing algorithms
to 3D is presented. This approach improves three-dimensional networkon-
chip (3D NoC) routing adaptivity while ensuring deadlock-freeness.
Finally, the proposed thermal-adaptive routing is implemented in
field-programmable gate array (FPGA), and implementation challenges,
for both thermal sensing and the dynamic control architecture are addressed.
The proposed routing implementation is evaluated in terms
of both functionality and performance.
The methodologies and architectures proposed in this thesis open a
new direction for improving the power and thermal integrity of future
NoC-based 2D and 3D many-core architectures
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