Stability, Causality, and Passivity in Electrical Interconnect Models

Modern packaging design requires extensive signal integrity simulations in order to assess the electrical performance of the system. The feasibility of such simulations is granted only when accurate and efficient models are available for all system parts and components having a significant influence on the signals. Unfortunately, model derivation is still a challenging task, despite the extensive research that has been devoted to this topic. In fact, it is a common experience that modeling or simulation tasks sometimes fail, often without a clear understanding of the main reason. This paper presents the fundamental properties of causality, stability, and passivity that electrical interconnect models must satisfy in order to be physically consistent. All basic definitions are reviewed in time domain, Laplace domain, and frequency domain, and all significant interrelations between these properties are outlined. This background material is used to interpret several common situations where either model derivation or model use in a computer-aided design environment fails dramatically.We show that the root cause for these difficulties can always be traced back to the lack of stability, causality, or passivity in the data providing the structure characterization and/or in the model itsel

Development of a new trigger system for spin-filtering studies

Polarized antiprotons allow unique access to a number of fundamental physics observables. One example is the transversity distribution which is the last missing piece to complete the knowledge of the nucleon partonic structure at leading twist in the QCD-based parton model. The transversity is directly measurable via Drell-Yan production in double polarized antiproton-proton collisions. This and a multitude of other findings, which are accessible via ~p ~p scattering experiments, led the Polarized Antiproton eXperiments (PAX) Collaboration to propose such investigations at the High Energy Storage Ring (HESR) of the Facility for Antiproton and Ion Research (FAIR). Futhermore the production of intense polarized antiproton beams is still an unsolved problem, which is the core of the PAX proposal. In this frame, an intense work on the feasibility of this ambitious project is going on at COSY (COoler SYnchrotron of the Institut für KernPhysik –IKP– of the Forschungs Zentrum Jülich) (FZJ) where the work of this thesis has been performed. Presently, the only available method to polarize an antiproton beam is by means of the mechanism of spin-filtering exploiting the spin dependence of the (p p) interaction via the repeated interaction with a polarized hydrogen target. Since the total cross section is different for parallel and antiparallel orientation of the beam particle spins relative to the direction of the target polarization, one spin direction is depleted faster than the other, so that the circulating beam becomes increasingly polarized, while the intensity decreases with time. A spin-filtering experiment with protons has been prepared and finally realized in 2011 at the COSY ring in Jülich. Aims of the spin-filtering experiments at COSY performed by the PAX Collaboration were two. The first was to confirm the present understanding of the spin filtering processes in storage rings, and the second was the commissioning of the experimental setup, which will be used for the experiments with the antiprotons. The major part of my PhD work consisted in the development and commissioning of a new trigger board to be implemented in the Data Acquisition System (DAQ) of the experiment. The motivation for the project was the replacement of the existing old-fashioned trigger system based on NIM logic modules, with a modern system based on FPGA programmable chips. This, also in perspective of the more complex detection system that the Collaboration is planning to realize for the future experimental activity. The trigger board was designed and realized by the electronic workshop of the University of Ferrara and INFN of Ferrara. My first task was to write the control-software of the board. After that I performed a series of development and commissioning tests which successfully demonstrated the full efficiency of the board and gave green light for the implementation of the board in the experimental setup

ATPG for Faults Analysis in VLSI Circuits Using Immune Genetic Algorithm

As design trends move toward nanometer technology, new Automatic Test Pattern Generation (ATPG)problems are merging. During design validation, the effect of crosstalk on reliability and performance cannot be ignored. So new ATPG Techniques has to be developed for testing crosstalk faults which affect the timing behaviour of circuits. In this paper, we present a Genetic Algorithm (GA) based test generation for crosstalk induced delay faults in VLSI circuits. The GA produces reduced test set which contains as few as possible test vector pairs, which detect as many as possible crosstalk delay faults. It uses a crosstalk delay fault simulator which computes the fitness of each test sequence. Tests are generated for ISCAS’85 and scan version of ISCAS’89 benchmark circuits. Experimental results demonstrate that GA gives higher fault coverage and compact test vectors for most of the benchmark circuits

Characterisation of crosstalk defects in submicron CMOS VLSI interconnects

The main problem addressed in this research work is a crosstalk defect, which is defined as an unexpected signal change due to the coupling between signals or power lines. Here its characteristic under 3 proposed models is investigated to find whether such a noise could lead to real logic faults in IC systems. As a result, mathematical analysis for various bus systems was established, with 3 main factors found to determine the amount of crosstalk: i) how the input buffers are sized; ii) the physical arrangements of the tracks; and iii) the number of switching tracks involved. Minimum sizes of the width and separation lead to the highest crosstalk while increasing in the length does not contribute much variation. Higher level of crosstalk is also found in higher metal layers due mainly to the reduced capacitance to the substrate. The crosstalk is at its maximum when the track concerned is the middle track of a bus connected to a weak buffer while the other signal lines are switching. From this information, the worse-case analysis for various bus configurations is proposed for 0.7, 0.5 and 0.35 µ CMOS technologies. For most of conventional logic circuits, a crosstalk as large as about a half of the supply voltage is required if a fault is to occur. For the buffer circuits the level of crosstalk required depends very much on the transition voltage, which is in turn controlled by the sizing of its n and p MOS transistors forming the buffer. It is concluded that in general case if crosstalk can be kept to be no larger that 30% of the supply voltage the circuit can be said to be very reliable and virtually free from crosstalk fault. Finally test structures are suggested so that real measurements can be made to verify the simulation result

Static noise margin analysis for CMOS logic cells in near-threshold

The advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing new impediments related to energy and power dissipation. Besides, the increasing demand for portable devices leads the circuit design paradigm to prioritize energy efficiency instead of performance. Altogether, this scenario motivates engineers towards reducing the supply voltage to the near and subthreshold regime to increase the lifespan of battery-powered devices. Even though operating in these regime offer interesting energy-frequency trade-offs, it brings challenges concerning noise tolerance. As the supply voltage reduces, the available noise margins decrease, and circuits become more prone to functional failures. In addition, near and subthreshold circuits are more susceptible to manufacturing variability, hence further aggravating noise issues. Other issues, such as wire minimization and gate fan-out, also contribute to the relevance of evaluating the noise margin of circuits early in the design Accordingly, this work investigates how to improve the static noise margin of digital synchronous circuits that will operate at the near/subthreshold regime. This investigation produces a set of three original contributions. The first is an automated tool to estimate the static noise margin of CMOS combinational cells. The second contribution is a realistic static noise margin estimation methodology that considers process-voltage-temperature variations. Results show that the proposed methodology allows to reduce up to 70% of the static noise margin pessimism. Finally, the third contribution is the noise-aware cell design methodology and the inclusion of a noise evaluation of complex circuits during the logic synthesis. The resulting library achieved higher static noise margin (up to 24%) and less spread among different cells (up to 62%).Os avanços na tecnologia de semicondutores possibilitou que se fabricasse dispositivos com atividade de chaveamento mais rápida e com maior capacidade de integração de transistores. Estes avanços, todavia, impuseram novos empecilhos relacionados com a dissipação de potência e energia. Além disso, a crescente demanda por dispositivos portáteis levaram à uma mudança no paradigma de projeto de circuitos para que se priorize energia ao invés de desempenho. Este cenário motivou à reduzir a tensão de alimentação com qual os dispositivos operam para um regime próximo ou abaixo da tensão de limiar, com o objetivo de aumentar sua duração de bateria. Apesar desta abordagem balancear características de performance e energia, ela traz novos desafios com relação a tolerância à ruído. Ao reduzirmos a tensão de alimentação, também reduz-se a margem de ruído disponível e, assim, os circuitos tornam-se mais suscetíveis à falhas funcionais. Somado à este efeito, circuitos com tensões de alimentação nestes regimes são mais sensíveis à variações do processo de fabricação, logo agravando problemas com ruído. Existem também outros aspectos, tais como a miniaturização das interconexões e a relação de fan-out de uma célula digital, que incentivam a avaliação de ruído nas fases iniciais do projeto de circuitos integrados Por estes motivos, este trabalho investiga como aprimorar a margem de ruído estática de circuitos síncronos digitais que irão operar em tensões no regime de tensão próximo ou abaixo do limiar. Esta investigação produz um conjunto de três contribuições originais. A primeira é uma ferramenta capaz de avaliar automaticamente a margem de ruído estática de células CMOS combinacionais. A segunda contribuição é uma metodologia realista para estimar a margem de ruído estática considerando variações de processo, tensão e temperatura. Os resultados obtidos mostram que a metodologia proposta permitiu reduzir até 70% do pessimismo das margens de ruído estática, Por último, a terceira contribuição é um fluxo de projeto de células combinacionais digitais considerando ruído, e uma abordagem para avaliar a margem de ruído estática de circuitos complexos durante a etapa de síntese lógica. A biblioteca de células resultante deste fluxo obteve maior margem de ruído (até 24%) e menor variação entre diferentes células (até 62%)

Analysis of acoustic communication channel characterization data in the surf zone

Submitted in partial fulfillment of the requirements for the degree of Master of Science at the Massachusetts Institute of Technology and the Woods Hole Oceanographic Institution September 2000A channel characterization experiment for the underwater acoustic communication channel was carried out at Scripps Pier in May 1999. The experiment investigated acoustic transmission in very shallow water and breaking waves. In analyzing the data, several questions arose. The majority of the acoustic channel probe data was corrupted by crosstalk in the receiver array cable. This thesis investigates methods to correct for the effects of the crosstalk, to attempt to recover the channel probe data. In selected regions, the crosstalk could be removed quite effectively using a linear least-squares method to estimate the crosstalk coefficients. The bulk of the data could not be corrected, however, primarily due to crosstalk from a receiver channel which was not recorded, and hence could not be well estimated. A second question addressed by this thesis is concerned with acoustic propagation in shallow water under bubble clouds. The breaking waves injected air deep into the water column. The resulting bubble clouds heavily attenuated acoustic signals, effectively causing total dropouts of the acoustic communication channel. Due to buoyancy, the bubbles gradually rise, and the communication channel clears. The channel clearing was significantly slower than predicted by geometric ray acoustic propagation models, however. Proposed explanations included secondary, unobserved, breaking events causing additional bubble injection; delayed rising of bubbles due to turbulent currents; or failure of the geometric ray model due to suppression by bubble clouds of acoustic signals which are not along the geometric ray paths. This thesis investigated the final hypothesis, modeling the acoustic propagation in Scripps Pier environment, using the full wave equation modeling package OASES. It was determined that the attenuation of the propagating acoustic signal is not accurately predicted by the bubble-induced attenuation along the geometric ray path.For financial support, thanks to the National Science Foundation for funding me on a Graduate Research Fellowship, and thanks to the WHOI Education Office for supplementing that fellowship

Physical Layer Modeling and Optimization of Silicon Photonic Interconnection Networks

The progressive blooming of silicon photonics technology (SiP) has indicated that optical interconnects may substitute the electrical wires for data movement over short distances in the future. Silicon Photonics platform has been the subject of intensive research for more than a decade now and its prospects continue to emerge as it enjoys the maturity of CMOS manufacturing industry. SiP foundries all over the world and particularly in the US (AIM Photonics) have been developing reliable photonic design kits (PDKs) that include fundamental SiP building blocks such as wavelength selective modulators and tunable filters. Microring resonators (MRR) are hailed as the most compact devices that can perform both modulation and demodulation in a wavelength division multiplexed (WDM) transceiver design. Although the use of WDM can reduce the number of fibers carrying data, it also makes the design of transceivers challenging. It is probably acceptable to achieve compactness at the expense of somewhat higher transceiver cost and power consumption. Nevertheless, these two metrics should remain close to their roadmap values for Datacom applications. An increase of an order of magnitude is clearly not acceptable. For example costs relative to bandwidth for an optical link in a data center interconnect will have to decrease from the current $5/Gbps down to <$1/Gbps. Additionally, the transceiver itself must remain compact. The optical properties of SiP devices are subject to various design considerations, operation conditions, and optimization procedures. In this thesis, the general goal is to develop mathematical models that can accurately describe the thermo-optical and electro-optical behavior of individual SiP devices and then use these models to perform optimization on the parameters of such devices to maximize the capabilities of photonic links or photonic switch fabrics for datacom applications. In Chapter 1, Introduction, we first provide an overview of the current state of the optical transceivers for data centers and datacom applications. Four main categories for optical interfaces (Pluggable transceivers, On-board optics, Co-packaged optics, monolithic integration) are briefly discussed. The structure of a silicon photonic link is also briefly introduced. Then the direction is shifted towards optical switching technologies where various technologies such as free space MEMS, liquid crystal on silicon (LCOS), SOA-based switches, and silicon-based switches are explored. In Chapter 2, Silicon Photonic Waveguides, we present an extensive study of the silicon-on-insulator (SOI) waveguides that are the basic building blocks of all of the SiP devices. The dispersion of Si and SiO2 is modeled with Sellmiere equation for the wavelength range 1500–1600 nm and then is used to calculate the TE and TM modes of a 2D slab waveguide. There are two reasons that 2D waveguides are studied: first, the modes of these waveguides have closed form solutions and the modes of 3D waveguides can be approximated from 2D waveguides based on the effective index method. Second, when the coupling of waveguides is studied and the concept of curvature function of coupling is developed, the coupled modes of 2D waveguides are used to show that this approach has some inherent small error due to the discretization of the nonuniform coupling. This chapter finishes by describing the coefficients of the sensitivity of optical modes of the waveguides to the geometrical and material parameters. Perturbation theory is briefly presented as a way to analytically examine the impact of small perturbations on the effective index of the modes. In Chapter 3, Compact Modeling Approach, the concept of scattering matrix of a multi-port silicon photonic device is presented. The elements of the S-matrix are complex numbers that relate the amplitude and phase relationships of the optical models in the input and output ports. Based on the scattering matrix modeling of silicon photonics devices, two methods of solving photonic circuits are developed: the first one is based on the iteration for linear circuits. The second approach is based on the construction of an equivalent signal flow graph (SFG) for the circuit. We show that the SFG approach is very efficient for circuits involving microring resonator structures. Not only SFG can provide the solution for the transmission, it also provides the signal paths and the closed-form solution based on the Mason’s graph formula. We also show how the SFG method can be utilized to formulate the backscattering effects inside a ring resonator. In Chapter 4, Scalability of Silicon Photonic Switch Fabrics, we develop the models for electro-optic Mach-Zehnder switch elements (2×2). For the electro-optic properties, the empirical Soref’s equations are used to characterize how the loss and index of silicon changes when the charge carrier density is changed. We then use our photonic circuit solver based on the iteration method to find accurate result of light propagation in large-scale switch topologies (e.g. 4×4, and 8×8). The concept of advanced path mapping based on physical layer evaluation of the switch fabric is introduced and used to develop the optimum routing tables for 4×4 and 8×8 Benes switch topologies. In Chapter 5, Design space of Microring Resonators, we introduce the concept of curvature function of coupling to mathematically characterize the coupling coefficient of a ring resonator to a waveguide as a function of the geometrical parameters (ring radius, coupling gap, width and height of waveguides) and the wavelength. Extensive 2D and 3D FDTD simulations are carried out to validate our modeling approach. Experimental demonstrations are also used to not only further validate our modeling of coupling, but also to extract an empirical power-law model for the bending loss of the ring resonators as a function the radius. By combining these models, we for the first time present a full characterization of the design space of microring resonators. Moreover, the value of this discussion will be further apparent when the scalability of a silicon photonic link is studied. We will show that the FSR of the rings determines the optical bandwidth but it also impacts the properties of the ring resonators. In Chapter 6, Thermo-optic Efficiency of Microheaters, we develop analytical models for the thermo-optic properties of SiP waveguides. For the thermo-optic properties, the concept of thermal impulse response is mathematically developed for integrated micro-heaters. The thermal impulse response is a key function that determines the tradeoff between heating efficiency and heating speed (thermal bandwidth), as well as allows us to predict the pulse-width-modulation (PWM) optical response of the heater-waveguide system. One of the motivations behind this study was to find the highest possible efficiency for thermal tuning of microring resonators to use it in the evaluation of the energy consumption of a photonic link. The results indicate 2 nm/mW which is in agreement with the trends that we see in the literature. In Chapter 7, Crosstalk Penalty, we theoretically and experimentally investigate the optical crosstalk effects in microring-based silicon photonic interconnects. Both inter-channel crosstalk and intra-channel crosstalk are investigated and approximate equations are developed for their corresponding power penalties. Inclusion of the inter-channel crosstalk is an important part of our final analysis of a silicon photonic link. In Chapter 8, Scalability of Silicon Photonic Links, we present the analysis of a WDM silicon photonics point-to-point link based on microring modulators and microring wavelength filters. Our approach is based on the power penalty analysis of non-return-to-zero (NRZ) signals and Gaussian noise statistics. All the necessary equations for the optical power penalty calculations are presented for microring modulators and filters. The first part of the analysis is based on various ideal assumptions which lead to a maximum capacity of 2.1 Tb/s for the link. The second part of the analysis is carried out with more realistic assumptions on the photonic elements in the link, culminating in a maximum throughput of 800 Gb/s. We also provide estimations of the energy/bit metric of such links based on the optimized models of electronic circuits in 65 nm CMOS technology

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast

Performance improvement of professional printing systems : from theory to practice

Performance Improvement of Professional Printing Systems: from theory to practice Markets demand continuously for higher quality, higher speed, and more energy-efficient professional printers. In this thesis, control strategies have been developed to improve the performance of both professional inkjet and laser printers. Drop-on-Demand (DoD) inkjet printing is considered as one of the most promising printing technologies. It offers several advantages including high speed, quiet operation, and compatibility with a variety of printing media. Nowadays, it has been used as low-cost and efficient manufacturing technology in a wide variety of markets. Although the performance requirements, which are imposed by the current applications, are tight, the future performance requirements are expected to be even more challenging. Several requirements are related to the jetted drop properties, namely, drop velocity, drop volume, drop velocity consistency, productivity, and reliability. Meeting the performance requirements is restricted by several operational issues that are associated with the design and operation of inkjet printheads. Major issues that are usually encountered are residual vibrations in and crosstalk among ink channels. This results in a poor printing quality for high-speed printing. Given any arbitrary bitmap, the main objective is to design actuation pulses such that variations in the velocity and volume of the jetted drops are minimized. Several model-based feedfoward control techniques using an existing model are implemented to generate appropriate input pulses for the printhead. Although the implementation of the model-based techniques shows a considerable improvement of the printhead performance compared with the current performance, further improvements are still necessary. We observe that besides the pulse shape the state of the ink surface at the nozzle plate (speed, position) at the start of the pulse influences the drop velocity considerably. This state at firing depends also on previous pixels in the bitmap of the image. Consequently, any pulse design has to guarantee almost the same initial state when firing a drop. Based on these facts, a model-free optimization scheme is developed to minimize the drop velocity variations taking into account the bitmap information. Experimental results show the effectiveness of the optimized pulses. Laser printing systems are highly depending on the appropriate combination of several design factors so as to become functional in a desired working range. The physical printing process involves multiple temperature set points at different places, precise electro-magnetic conditions, transfer of toner through certain pressures and layouts, and many other technical considerations. In the laser printing system there are several challenging issues and unknown disturbances. They originate from different sources, such as the printer itself (unknown phenomena appear, disturbances that are not foreseen, wear, contamination, failures, bugs), the environment of the system (power supply variations, temperature, humidity, vibrations), and the printing media (weight, coating, thermal properties, humidity characteristics, and initial temperature). These issues have a negative effect on the stability and performance of the laser printing system. The objective is to design a control scheme to achieve printing quality requirements and a high productivity. Good printing quality means that the fusing temperature should track a certain reference signal at different operating conditions. Based on the printing system behavior, we propose two different control schemes to cope with the large parameter variations and disturbances, namely, a Model Reference Adaptive Controller (MRAC) and a nonlinear (scheduled) observer-based output feedback control scheme. Both control techniques yield considerable performance improvements compared with the present industrial controller