61,518 research outputs found

    Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits

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    We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.Ministerio de Educación y Ciencia TEC2006-03022Junta de Andalucía TIC-0281

    AutoAccel: Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture

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    CPU-FPGA heterogeneous architectures are attracting ever-increasing attention in an attempt to advance computational capabilities and energy efficiency in today's datacenters. These architectures provide programmers with the ability to reprogram the FPGAs for flexible acceleration of many workloads. Nonetheless, this advantage is often overshadowed by the poor programmability of FPGAs whose programming is conventionally a RTL design practice. Although recent advances in high-level synthesis (HLS) significantly improve the FPGA programmability, it still leaves programmers facing the challenge of identifying the optimal design configuration in a tremendous design space. This paper aims to address this challenge and pave the path from software programs towards high-quality FPGA accelerators. Specifically, we first propose the composable, parallel and pipeline (CPP) microarchitecture as a template of accelerator designs. Such a well-defined template is able to support efficient accelerator designs for a broad class of computation kernels, and more importantly, drastically reduce the design space. Also, we introduce an analytical model to capture the performance and resource trade-offs among different design configurations of the CPP microarchitecture, which lays the foundation for fast design space exploration. On top of the CPP microarchitecture and its analytical model, we develop the AutoAccel framework to make the entire accelerator generation automated. AutoAccel accepts a software program as an input and performs a series of code transformations based on the result of the analytical-model-based design space exploration to construct the desired CPP microarchitecture. Our experiments show that the AutoAccel-generated accelerators outperform their corresponding software implementations by an average of 72x for a broad class of computation kernels

    An Agent Operationalization Approach for Context Specific Agent-Based Modeling

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    The potential of agent-based modeling (ABM) has been demonstrated in various research fields. However, three major concerns limit the full exploitation of ABM; (i) agents are too simple and behave unrealistically without any empirical basis, (ii) \'proof of concept\' applications are too theoretical and (iii) too much value placed on operational validity instead of conceptual validity. This paper presents an operationalization approach to determine the key system agents, their interaction, decision-making and behavior for context specific ABM, thus addressing the above-mentioned shortcomings. The approach is embedded in the framework of Giddens\' structuration theory and the structural agent analysis (SAA). The agents\' individual decision-making (i.e. reflected decisions) is operationalized by adapting the analytical hierarchy process (AHP). The approach is supported by empirical system knowledge, allowing us to test empirically the presumed decision-making and behavioral assumptions. The output is an array of sample agents with realistic (i.e. empirically quantified) decision-making and behavior. Results from a Swiss mineral construction material case study illustrate the information which can be derived by applying the proposed approach and demonstrate its practicability for context specific agent-based model development.Agent Operationalization, Decision-Making, Analytical Hierarchy Process (AHP), Agent-Based Modeling, Conceptual Validation

    Comprehensive and modular stochastic modeling framework for the variability-aware assessment of Signal Integrity in high-speed links

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    This paper presents a comprehensive and modular modeling framework for stochastic signal integrity analysis of complex high-speed links. Such systems are typically composed of passive linear networks and nonlinear, usually active, devices. The key idea of the proposed contribution is to express the signals at the ports of each of such system elements or subnetworks as a polynomial chaos expansion. This allows one to compute, for each block, equivalent deterministic models describing the stochastic variations of the network voltages and currents. Such models are synthesized into SPICE-compatible circuit equivalents, which are readily connected together and simulated in standard circuit simulators. Only a single circuit simulation of such an equivalent network is required to compute the pertinent statistical information of the entire system, without the need of running a large number of time-consuming electromagnetic circuit co-simulations. The accuracy and efficiency of the proposed approach, which is applicable to a large class of complex circuits, are verified by performing signal integrity investigations of two interconnect examples
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