Silicon on ferroelectric insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Title from PDF of title page, viewed on March 12, 2014Thesis advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 116-131)Thesis (M. S.)--School of Computer and Engineering. University of Missouri--Kansas City, 2013Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in subnanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor’s Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-lowpower applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.Abstract -- List of illustrations - List of tables -- Acknowledgements -- Dedication -- Introduction -- Carbon nanotube field effect transistor -- Multi-gate transistors -FinFET -- Subthreshold swing -- Tunneling field effect transistors -- I-mos and nanowire fets -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for soi-finfet -- Silicon-on-ferroelectric insulator field effect transistor (SOF-FET) -- Current-voltage characteristics of sof-fet -- Advantages, manufacturing process and future work of the proposed device -- Appendix -- Reference

Silicon on Ferroelectric Insulator Field Effect Transistor (SOFFET): A Radical Alternative to Overcome the Thermionic Limit

Title from PDF of title page viewed January 3,2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 165-180)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2016The path of down-scaling traditional MOSFET is reaching its technological, economic and, most importantly, fundamental physical limits. Before the dead-end of the roadmap, it is imperative to conduct a broad research to find alternative materials and new architectures to the current technology for the MOSFET devices. Beyond silicon electronic materials like group III-V heterostructure, ferroelectric material, carbon nanotubes (CNTs), and other nanowire-based designs are in development to become the core technology for non-classical CMOS structures. Field effect transistors (FETs) in general have made unprecedented progress in the last few decades by down-scaling device dimensions and power supply level leading to extremely high numbers of devices in a single chip. High density integrated circuits are now facing major challenges related to power management and heat dissipation due to excessive leakage, mainly due to subthreshold conduction. Over the years, planar MOSFET dimensional reduction was the only process followed by the semiconductor industry to improve device performance and to reduce the power supply. Further scaling increases short-channel-effect (SCE), and off-state current makes it difficult for the industry to follow the well-known Moore’s Law with bulk devices. Therefore, scaling planar MOSFET is no longer considered as a feasible solution to extend this law. The down-scaling of metal-oxide-semiconductor field effect transistors (MOSFETs) leads to severe short-channel-effects and power leakage at large-scale integrated circuits (LSIs). The device, which is governed by the thermionic emission of the carriers injected from the source to the channel region, has set a limitation of the subthreshold swing (S) of 60 / at room temperature. Devices with ‘S’ below this limit is highly desirable to reduce the power consumption and maintaining a high / current ratio. Therefore, the future of semiconductor industry hangs on new architectures, new materials or even new physics to govern the flow of carriers in new switches. As the subthreshold swing is increasing at every technology node, new structures using SOI, multi-gate, nanowire approach, and new channel materials such as III–V semiconductor have not satisfied the targeted values of subthreshold swing. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic emission limit of 60 /. This value was unbreakable by the new structure (SOI FinFET). On the other hand, most of the preview proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for sub-60 mV/decade designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This dissertation also proposes a novel design that exploits the concept of negative capacitance. The new field-effect-transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field effect-transistor (SOFFET). This proposal is a promising methodology for future ultra low-power applications because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers a subthreshold swing significantly lower than 60 / and reduced threshold voltage to form a conducting channel. The proposed SOFFET design, which utilizes the negative capacitance of a ferroelectric insulator in the body-stack, is completely different from the FeFET and NCFET designs. In addition to having the NC effect, the proposed device will have all the advantages of an SOI device. Body-stack that we are intending in this research has many advantages over the gate-stack. First, it is more compatible with the existing processes. Second, the gate and the working area of the proposed SOFFET is like the planar MOSFET. Third, the complexity and ferroelectric material interferences are shifted to the body of the device from the gate and the working area. The proposed structure offers better scalability and superior constructability because of the high-dielectric buried insulator. Here we are providing a very simplified model for the structure. Silicon-on-ferroelectric leads to several advantages including low off-state current and shift in the threshold voltage with the decrease of the ferroelectric material thickness. Moreover, having an insulator in the body of the device increases the controllability over the channel, which leads to the reduction in the short-channel-effect (SCE). The proposed SOFFET offers low value of subthreshold swing (S) leading to better performance in the on-state. The off-state current is directly related to S. So, the off-state current is also minimum in the proposed structure.Introduction -- Subthreshold swing -- Multi-gate devices -- Tunneling field effect transistors -- I-mos & FET transistors -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for SOI-FINFET -- Multichannel tunneling carbon nanotube FET -- Partially depleted silicon-on-Ferroelectric insulator FET -- Fully depleted silicon-on-ferroelectric insulator FET -- Advantages, manufacturing process, and future work of the proposed devices -- Appendix A. Estimation of the body factor (n) [eta] of SOI FinFET -- Appendix B. Solution for the Poisson Equation of MT-CNTFE

Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies

Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio

Power system applications of fiber optics

Power system applications of optical systems, primarily using fiber optics, are reviewed. The first section reviews fibers as components of communication systems. The second section deals with fiber sensors for power systems, reviewing the many ways light sources and fibers can be combined to make measurements. Methods of measuring electric field gradient are discussed. Optical data processing is the subject of the third section, which begins by reviewing some widely different examples and concludes by outlining some potential applications in power systems: fault location in transformers, optical switching for light fired thyristors and fault detection based on the inherent symmetry of most power apparatus. The fourth and final section is concerned with using optical fibers to transmit power to electric equipment in a high voltage situation, potentially replacing expensive high voltage low power transformers. JPL has designed small photodiodes specifically for this purpose, and fabricated and tested several samples. This work is described

ULTRARAM™:Design, Modelling, Fabrication and Testing of Ultra-low-power III-V Memory Devices and Arrays

In this thesis, a novel memory based on III-V compound semiconductors is studied, both theoretically and experimentally, with the aim of developing a technology with superior performance capabilities to established and emerging rival memories. This technology is known as ULTRARAM™. The memory concept is based on quantum resonant tunnelling through InAs/AlSb heterostructures, which are engineered to only allow electron tunnelling at precise energy alignment(s) when a bias is applied. The memory device features a floating gate (FG) as the storage medium, where electrons that tunnel through the InAs/AlSb heterostructure are confined in the FG to define the memory logic (0 or 1). The large conduction band offset of the InAs/AlSb heterojunction (2.1 eV) keeps electrons in the FG indefinitely, constituting a non-volatile logic state. Electrons can be removed from the FG via a similar resonant tunnelling process by reversing the voltage polarity. This concept shares similarities with flash memory, however the resonant tunnelling mechanism provides ultra-low-power, low-voltage, high-endurance and high-speed switching capability. The quantum tunnelling junction is studied in detail using the non-equilibrium Green’s function (NEGF) method. Then, Poisson-Schrödinger simulations are used to design a high-contrast readout procedure for the memory using the unusual type-III band-offset of the InAs/GaSb heterojunction. With the theoretical groundwork for the technology laid out, the memory performance is modelled and a high-density ULTRARAM™ memory architecture is proposed for random-access memory applications. Later, NEGF calculations are used for a detailed study of the process tolerances in the tunnelling region required for ULTRARAM™ large-scale wafer manufacture. Using interfacial misfit array growth techniques, III-V layers (InAs, AlSb and GaSb) for ULTRARAM™ were successfully implemented on both GaAs and Si substrates. Single devices and 2×2 arrays were then fabricated using a top-down processing approach. The memories demonstrated outstanding memory performance on both substrate materials at 10, 20 and 50 µm gate lengths at room temperature. Non-volatile switching was obtained with ≤ 2.5 V pulses, corresponding to a switching energy per unit area that is lower than DRAM and flash by factors of 100 and 1000 respectively. Memory logic was retained for over 24 hours whilst undergoing over 10^6 readout operations. Analysis of the retention data suggests a storage time exceeding 1000 years. Devices showed promising durability results, enduring over 10^7 cycles without degradation, at least two orders of magnitude improvement over flash memory. Switching of the cell’s logic was possible at 500 µs pulse durations for a 20 µm gate length, suggesting a subns switching time if scaled to modern-day feature sizes. The proposed half-voltage architecture is shown to operate in principle, where the memory state is preserved during a disturbance test of > 10^5 half-cycles. With regard to the device physics, these findings point towards ULTRARAM™ as a universal memory candidate. The path towards future commercial viability relies on process development for aggressive device and array-size scaling and implementation on larger Si wafe

Feature Papers in Electronic Materials Section

This book entitled "Feature Papers in Electronic Materials Section" is a collection of selected papers recently published on the journal Materials, focusing on the latest advances in electronic materials and devices in different fields (e.g., power- and high-frequency electronics, optoelectronic devices, detectors, etc.). In the first part of the book, many articles are dedicated to wide band gap semiconductors (e.g., SiC, GaN, Ga2O3, diamond), focusing on the current relevant materials and devices technology issues. The second part of the book is a miscellaneous of other electronics materials for various applications, including two-dimensional materials for optoelectronic and high-frequency devices. Finally, some recent advances in materials and flexible sensors for bioelectronics and medical applications are presented at the end of the book

NASA Tech Briefs, March 1996

Topics: Computer-Aided Design and Engineering; Electronic Components and Cicuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery/Automation; Manufacturing/Fabrication; Mathematics and Information; Books and Reports

Estudo de materiais multiferroicos

Doutoramento em FísicaThe present PhD work aims the research and development of materials that exhibit multiferroic properties, in particular having a significant interaction between ferromagnetism and ferroelectricity; either directly within an intrinsic single phase or by combining extrinsic materials, achieving the coupling of properties through mechanic phenomena of the respective magnetostriction and piezoelectricity. These hybrid properties will allow the cross modification of magnetic and electric polarization states by the application of cross external magnetic and/or electric fields, giving way to a vast area for scientific investigation and potential technological applications in a new generation of electronic devices, such as computer memories, signal processing, transducers, sensors, etc. Initial experimental work consisted in chemical synthesis of nano powders oxides by urea pyrolysis method: A series of ceramic bulk composites with potential multiferroic properties comprised: of LuMnO3 with La0.7Sr0.3MnO3 and BaTiO3 with La0.7Ba0.3MnO3; and a series based on the intrinsic multiferroic LuMn1-zO3 phase modified with of Manganese vacancies. The acquisition of a new magnetron RF sputtering deposition system, in the Physics Department of Aveiro University, contributed to the proposal of an analogous experimental study in multiferroic thin films and multilayer samples. Besides the operational debut of this equipment several technical upgrades were completed like: the design and construction of the heater electrical contacts; specific shutters and supports for the magnetrons and for the substrate holder and; the addition of mass flow controllers, which allowed the introduction of N2 or O2 active atmosphere in the chamber; and the addition of a second RF generator, enabling co-deposition of different targets. Base study of the deposition conditions and resulting thin films characteristics in different substrates was made from an extensive list of targets. Particular attention was given to thin film deposition of magnetic phases La1-xSrxMnO3, La1-xBaxMnO3 and Ni2+x-yMn1-xGa1+y alloy, from the respective targets: La0.7Sr0.3MnO3, La0.7Ba0.3MnO3; and NiGa with NiMn. Main structural characterization of samples was performed by conventional and high resolution X-Ray Diffraction (XRD); chemical composition was determined by Electron Dispersion Spectroscopy (EDS); magnetization measurements recur to a Vibrating Sample Magnetometer (VSM) prototype; and surface probing (SPM) using Magnetic-Force (MFM) and Piezo-Response (PFM) Microscopy. Results clearly show that the composite bulk samples (LuM+LSM and BTO+LBM) feat the intended quality objectives in terms of phase composition and purity, having spurious contents below 0.5 %. SEM images confirm compact grain packaging and size distribution around the 50 nm scale. Electric conductivity, magnetization intensity and magneto impedance spreading response are coherent with the relative amount of magnetic phase in the sample. The existence of coupling between the functional phases is confirmed by the Magnetoelectric effect measurements of the sample “78%LuM+22%LSM” reaching 300% of electric response for 1 T at 100 kHz; while in the “78%BTO+22%LBM” sample the structural transitions of the magnetic phase at ~350 K result in a inversion of ME coefficient the behavior. A functional Magneto-Resistance measurement system was assembled from the concept stage until the, development and operational status; it enabled to test samples from 77 to 350 K, under an applied magnetic field up to 1 Tesla with 360º horizontal rotation; this system was also designed to measure Hall effect and has the potential to be further upgraded. Under collaboration protocols established with national and international institutions, complementary courses and sample characterization studies were performed using Magneto-Resistance (MR), Magneto-Impedance (MZ) and Magneto-Electric (ME) measurements; Raman and X-ray Photoelectron Spectroscopy (XPS); SQUID and VSM magnetization; Scanning Electron Microscopy (SEM) and Rutherford Back Scattering (RBS); Scan Probe Microscopy (SPM) with Band Excitation Probe Spectroscopy (BEPS); Neutron Powder Diffraction (NPD) and Perturbed Angular Correlations (PAC). Additional collaboration in research projects outside the scope of multiferroic materials provided further experience in sample preparation and characterization techniques, namely VSM and XPS measurements were performed in cubane molecular complex compounds and enable to identify the oxidation state of the integrating cluster of Ru ions; also, XRD and EDS/SEM analysis of the acquired targets and substrates implied the devolution of some items not in conformity with the specifications. Direct cooperation with parallel research projects regarding multiferroic materials, enable the assess to supplementary samples, namely a preliminary series of nanopowder Y1-x-yCaxØyMn1O3 and of Eu0.8Y0.2MnO3, a series of micropowder composites of LuMnO3 with La0.625Sr0.375MnO3 and of BaTiO3 with hexagonal ferrites; mono and polycrystalline samples of Pr1-xCaxMnO3, La1-xSrxMnO3 and La1-xCaxMnO3.O trabalho de doutoramento presente tem por objectivo a pesquisa e desenvolvimento de materiais que manifestem propriedades multiferróicas, em particular com uma significativa interacção entre os fenómenos de ferromagnetismo e ferroelectricidade; seja de forma intrínseca em determinados materiais singulares, ou extrínseca ao combinar materiais que apresentam respectivamente fenómenos magnetoestritivo e de piezoelectricidade e em que geralmente o acoplamento se processa mecanicamente entre as fases. Esta hibridação de propriedades permite a modificação dos estados de polarização magnética ou eléctrica por aplicação dos campos externos complementares (eléctricos e/ou magnéticos), dando origem a uma vasta área de investigação científica e potenciais aplicações tecnológicas numa nova geração de dispositivos electrónicos como memórias, processadores, transdutores, sensores, etc. O trabalho experimental inicial consistiu na síntese química de óxidos sob a forma de pós nanométricos, pelo método de pirólise da ureia; As séries de compósitos maciços com potenciais propriedades multiferróicas compreendem: LuMnO3 com La0.7Sr0.3MnO3 e BaTiO3 com La0.7Ba0.3MnO3; e uma série baseada na modificação com lacunas de Manganésio da fase multiferróica intrínseca LuMn1-zO3. A aquisição de um novo sistema de deposição por RF sputtering, no Departamento de Física da Universidade de Aveiro, contribuiu para a proposta de estudo análogo de amostras multiferróicas sob a forma de filmes finos e multicamadas. Além da estreia operacional do equipamento foram efectuadas algumas melhorias técnicas e funcionais de que se destacam: o desenho e construção das ligações eléctricas do aquecedor; de portadas, protecções e respectivos suportes para os magnetrões e para o “porta substratos”; a adição de dois controladores de fluxo de gás permitindo a introdução controlada de Árgon e de atmosfera activa de O2 ou N2 durante a deposição; e a adição de uma segunda fonte e controlador RF permitindo a co-deposição simultânea de filmes a partir de dois alvos diferentes. O estudo base sobre as condições de deposição e das características dos filmes finos resultantes em diferentes substratos foi efectuada a partir de uma extensa lista de alvos. Atenção particular foi dada à deposição de filmes finos das fases magnéticas de La1-xSrxMnO3, La1-xBaxMnO3 e da liga Ni2+x-yMn1-xGa1+y a partir dos correspondentes alvos La0.7Sr0.3MnO3; La0.7Ba0.3MnO3 e NiGa com NiMn. A caracterização estrutural das amostras foi efectuada com Difractometria por Raios-X (XRD) convencional e de elevada resolução; determinação da composição química foi essencialmente realizada por Espectroscopia de Dispersão de Electrões (EDS); medidas de magnetização foram executadas com recurso a um protótipo de Magnetometro por Vibração da Amostra (VSM) e as medidas de análise de superfície utilizaram Microscopia de Ponta (SPM) nas vertentes de piezo resposta (PFM) e de força magnética (MFM). Os resultados obtidos nos compósitos maciços (LuM+LSM e BTO+LBM) demonstram claramente que as amostras satisfazem os objectivos propostos em termos de composição pureza das fases, com eventual conteúdo em óxidos espúrios inferior a 0.5%. Imagens obtidas por SEM confirmam a compactação dos grãos e distribuição de tamanhos em torno dos 50 nm. Condutividade eléctrica, intensidade da magnetização e a dispersão da resposta em Magneto-Impedância são coerentes com a proporção relativa da fase magnética em cada amostra. A existência de um acoplamento entre as fases funcionais é evidenciada por medidas de efeito Magneto-Eléctrico na amostra “78%LuM+22%LSM” que apresenta uma resposta eléctrica de ~300% para 1 Tesla a 100 kHz; enquanto que na amostra “78%BTO+22%LBM” se assinala a transição estrutural da fase magnética a ~350 K resulta na inversão do comportamento do coeficiente ME. Um sistema de Medidas de Magneto-Resistência foi totalmente desenvolvido e montado desde a fase conceptual até ao estado operacional; permite testar amostras de 77 a 350 K em função do campo magnético até 1 Tesla, e rotação horizontal de 360º; o sistema foi também desenhado para poder efectuar medidas de efeito de Hall e permitir upgrades. Ao abrigo de protocolos de colaboração estabelecidos com diversas instituições nacionais e internacionais, foram realizados cursos de formação complementar e caracterização de amostras em técnicas como Magneto Resistência (MR), Magneto Impedância (MZ) e efeito Magneto Eléctrico (ME); Espectroscopia Raman e Fotoelectrónica de Raios-X (XPS); Magnetização via sistemas SQUID e VSM; Microscopia de Ponta em Piezo resposta (PFM) e Espectroscopia de excitação em largura de banda (BEPS); Espectroscopia de Rutherford por Retro dispersão (RBS); Difracção de Neutrões em pós (NPD) e Correlações de Perturbação Angular (PAC) Colaboração em projectos de investigação fora do âmbito dos materiais multiferróicos permitiu ampliar e versatilizar experiencia em técnicas de preparação e caracterização de amostras, nomeadamente medidas de VSM e XPS permitiram identificar os estados de oxidação dos clusters de iões de Ruténio que integram complexos moleculares utilizados em catalisadores; A certificação por XRD e SEM/EDS do conjunto dos alvos e amostragem dos substratos adquiridos implicou a devolução de alguns itens com por falta de conformidade com as especificações. Cooperação directa em projectos de investigação paralelos sobre materiais multiferróicos permitiu o acesso a amostras suplementares, nomeadamente a uma série nano pós de Y1-x-yCaxØyMn1O3 e de Eu0.8Y0.2MnO3; a series de compósitos microestruturados de LuMnO3 com La0.625Sr0.375MnO3 e de BaTiO3 com ferrites hexagonais; e a diversas amostras poli- e mono-cristalinas de Pr1-xCaxMnO3, La1-xSrxMnO3 e La1-xCaxMnO3.FCT - SFRH/BD/25011/200