Synchrony breakdown and noise-induced oscillation death in ensembles of serially connected spin-torque oscillators

We consider collective dynamics in the ensemble of serially connected spin-torque oscillators governed by the Landau-Lifshitz-Gilbert-Slonczewski magnetization equation. Proximity to homoclinicity hampers synchronization of spin-torque oscillators: when the synchronous ensemble experiences the homoclinic bifurcation, the Floquet multiplier, responsible for the temporal evolution of small deviations from the ensemble mean, diverges. Depending on the configuration of the contour, sufficiently strong common noise, exemplified by stochastic oscillations of the current through the circuit, may suppress precession of the magnetic field for all oscillators. We derive the explicit expression for the threshold amplitude of noise, enabling this suppression.Comment: 12 pages, 13 figure

Voltage controlled oscillators for 40Gbit/s cascaded bit-interleaving PON

Technologies such as the Internet-of-Things and cloud services demand dynamic bandwidth allocation flexibility, which is not offered by the currently deployed solutions. The Bit-Interleaving PON (BiPON) and its cascaded extension the Cascaded Bit-Interleaving PON (CBI-PON) offer a solution that allows to increase bandwidths, reduce power consumption and have a much more flexible dynamic bandwidth allocation scheme. CBI-PON consists of multiple levels of BiPON with different line rates. For each of these line rates, clock-and-data recovery must be performed, which requires a set of different Voltage Controlled Oscillators (VCOs). This paper presents the VCOs designed for the CABINET chip, an implementation of a CBI-PON network device, allowing clock-and-data recovery for 40Gbit/s, 10 Gbit/s and 2.5 Gbit/s line rates

A general theory of phase noise in electrical oscillators

A general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators. This new approach also elucidates several previously unknown design criteria for reducing close-in phase noise by identifying the mechanisms by which intrinsic device noise and external noise sources contribute to the total phase noise. In particular, it explains the details of how 1/f noise in a device upconverts into close-in phase noise and identifies methods to suppress this upconversion. The theory also naturally accommodates cyclostationary noise sources, leading to additional important design insights. The model reduces to previously available phase noise models as special cases. Excellent agreement among theory, simulations, and measurements is observed

Basics of RF electronics

RF electronics deals with the generation, acquisition and manipulation of high-frequency signals. In particle accelerators signals of this kind are abundant, especially in the RF and beam diagnostics systems. In modern machines the complexity of the electronics assemblies dedicated to RF manipulation, beam diagnostics, and feedbacks is continuously increasing, following the demands for improvement of accelerator performance. However, these systems, and in particular their front-ends and back-ends, still rely on well-established basic hardware components and techniques, while down-converted and acquired signals are digitally processed exploiting the rapidly growing computational capability offered by the available technology. This lecture reviews the operational principles of the basic building blocks used for the treatment of high-frequency signals. Devices such as mixers, phase and amplitude detectors, modulators, filters, switches, directional couplers, oscillators, amplifiers, attenuators, and others are described in terms of equivalent circuits, scattering matrices, transfer functions; typical performance of commercially available models is presented. Owing to the breadth of the subject, this review is necessarily synthetic and non-exhaustive. Readers interested in the architecture of complete systems making use of the described components and devoted to generation and manipulation of the signals driving RF power plants and cavities may refer to the CAS lectures on Low-Level RF.Comment: 36 pages, contribution to the CAS - CERN Accelerator School: Specialised Course on RF for Accelerators; 8 - 17 Jun 2010, Ebeltoft, Denmar

Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage

Optimization study of high power static inverters and converters Final report

Optimization study and basic performance characteristics for conceptual designs for high power static inverter

A 5.9 GHz Low Power and Wide Tuning Range CMOS Current-controlled Ring Oscillator

Designing low power, low noise, wide tuning range and small size circuit in one single chip is very challenging. This paper describe a low power, wide tuning range three-stage current-controlled ring oscillator (CCO) designed on 0.18um CMOS technology. The CCO circuit has tuning range from 251 MHz to 5.5 GHz or 183% wide. It consumes only 144 uA to 9.76mA by using 1.8V power supply. Phase noise is -104 dBc /Hz at 5.5 GHz and 4 Mhz offset frequency.  Calculated FoM is -154.4 dBc /Hz which is the best among published counterpart papers. The size of the core oscillator circuits without bonding pads is only 0.0003 mm2.DOI:http://dx.doi.org/10.11591/ijece.v2i3.22