Noise Characterization and Filtering in the MicroBooNE Liquid Argon TPC

The low-noise operation of readout electronics in a liquid argon time projection chamber (LArTPC) is critical to properly extract the distribution of ionization charge deposited on the wire planes of the TPC, especially for the induction planes. This paper describes the characteristics and mitigation of the observed noise in the MicroBooNE detector. The MicroBooNE's single-phase LArTPC comprises two induction planes and one collection sense wire plane with a total of 8256 wires. Current induced on each TPC wire is amplified and shaped by custom low-power, low-noise ASICs immersed in the liquid argon. The digitization of the signal waveform occurs outside the cryostat. Using data from the first year of MicroBooNE operations, several excess noise sources in the TPC were identified and mitigated. The residual equivalent noise charge (ENC) after noise filtering varies with wire length and is found to be below 400 electrons for the longest wires (4.7 m). The response is consistent with the cold electronics design expectations and is found to be stable with time and uniform over the functioning channels. This noise level is significantly lower than previous experiments utilizing warm front-end electronics.Comment: 36 pages, 20 figure

Efficient DSP and Circuit Architectures for Massive MIMO: State-of-the-Art and Future Directions

Massive MIMO is a compelling wireless access concept that relies on the use of an excess number of base-station antennas, relative to the number of active terminals. This technology is a main component of 5G New Radio (NR) and addresses all important requirements of future wireless standards: a great capacity increase, the support of many simultaneous users, and improvement in energy efficiency. Massive MIMO requires the simultaneous processing of signals from many antenna chains, and computational operations on large matrices. The complexity of the digital processing has been viewed as a fundamental obstacle to the feasibility of Massive MIMO in the past. Recent advances on system-algorithm-hardware co-design have led to extremely energy-efficient implementations. These exploit opportunities in deeply-scaled silicon technologies and perform partly distributed processing to cope with the bottlenecks encountered in the interconnection of many signals. For example, prototype ASIC implementations have demonstrated zero-forcing precoding in real time at a 55 mW power consumption (20 MHz bandwidth, 128 antennas, multiplexing of 8 terminals). Coarse and even error-prone digital processing in the antenna paths permits a reduction of consumption with a factor of 2 to 5. This article summarizes the fundamental technical contributions to efficient digital signal processing for Massive MIMO. The opportunities and constraints on operating on low-complexity RF and analog hardware chains are clarified. It illustrates how terminals can benefit from improved energy efficiency. The status of technology and real-life prototypes discussed. Open challenges and directions for future research are suggested.Comment: submitted to IEEE transactions on signal processin

Single-Event Upset Analysis and Protection in High Speed Circuits

The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at the input of a flip-flop and consequently is latched in the flip-flop and generates a soft-error. When an SET conjoined with a transition at a node along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a flip-flop. On the other hand, increasing pipeline depth and using low power techniques such as multi-level power supply, and multi-threshold transistor convert almost all paths in a circuit to critical ones. Thus, studying the behavior of the SET in these kinds of circuits needs special attention. This paper studies the dynamic behavior of a circuit with massive critical paths in the presence of an SET. We also propose a novel flip-flop architecture to mitigate the effects of such SETs in combinational circuits. Furthermore, the proposed architecture can tolerant a single event upset (SEU) caused by particle strike on the internal nodes of a flip-flo

FDTD modeling of heatsink RF characteristics for EMC mitigation

Due to their size and complex geometry, large heatsinks such as those used in the power electronics industry may enhance the radiated emissions produced by the circuits employing them. Such enhancement of the radio frequency (rf) radiation could cause the equipment to malfunction or to contravene current EMC regulations. In this paper, the electromagnetic resonant effects of heatsinks are examined using the finite-difference time-domain (FDTD) method and recommendations are made concerning the optimum geometry of heatsinks and the placement of components so as to mitigate potential EMC effects