Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS

This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded ΔΣ modulator enables the power efficient implementation of multiple communication standards.@The advantages of multirate cascaded ΔΣ modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time ΔΣ modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode ΔΣ modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm2. Measurement results show a dynamic range of 66/77/85 dB for UMTS/ Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ

Optimum quantization of a class of non-bandlimited signals

We consider the quantization of a special class of non bandlimited signals, namely the class of discrete time signals that can be recovered from their decimated version. Similar to sigma-delta modulation ideas, we show that we can obtain a great reduction in the quantization noise variance due to the oversampled nature of these signals. We then consider noise shaping by optimizing a pre- and post filter around the quantizer and develop a closed form expression for the coding gain of the scheme under study. The use of an orthonormal filter bank as a sophisticated quantizer is investigated and several examples are provided

Oversampling PCM techniques and optimum noise shapers for quantizing a class of nonbandlimited signals

We consider the efficient quantization of a class of nonbandlimited signals, namely, the class of discrete-time signals that can be recovered from their decimated version. The signals are modeled as the output of a single FIR interpolation filter (single band model) or, more generally, as the sum of the outputs of L FIR interpolation filters (multiband model). These nonbandlimited signals are oversampled, and it is therefore reasonable to expect that we can reap the same benefits of well-known efficient A/D techniques that apply only to bandlimited signals. We first show that we can obtain a great reduction in the quantization noise variance due to the oversampled nature of the signals. We can achieve a substantial decrease in bit rate by appropriately decimating the signals and then quantizing them. To further increase the effective quantizer resolution, noise shaping is introduced by optimizing prefilters and postfilters around the quantizer. We start with a scalar time-invariant quantizer and study two important cases of linear time invariant (LTI) filters, namely, the case where the postfilter is the inverse of the prefilter and the more general case where the postfilter is independent from the prefilter. Closed form expressions for the optimum filters and average minimum mean square error are derived in each case for both the single band and multiband models. The class of noise shaping filters and quantizers is then enlarged to include linear periodically time varying (LPTV)M filters and periodically time-varying quantizers of period M. We study two special cases in great detail

VLSI Implementation of Cascaded Integrator Comb Filters for DSP Applications

The recursive comb filters or Cascaded Integrator Comb filter (CIC) are commonly used as decimators for the sigma delta modulators. This paper presents the VLSI implementation, analysis and design of high speed CIC filters which are based on a low-pass filter. These filters are used in the signal decimation which has the effect on reducing the sampling rate. It is also chosen because its attractive property of both low power and low complexity since it dose not required a multiplier. Simulink toolbox available in Matlab software which is used to simulator and Verilog HDL coding help to verify the functionality of the CIC filters. Design procedures and examples are given for CIC filter with emphasis on frequency response, transfer function and register width. The implementation results show using Modified Carry Look-ahead Adder for summation and also apply pipelined filter structure enhanced high speed and make it more compatible for DSP applications

Efficient Hybrid Continuous-Time/Discrete-Time Cascade Modulators for Wideband Applications

This paper analyses the use of hybrid continuous-time/discrete-time cascade ΣΔ modulators for the implementation of power-efficient analog-to-digital converters in broadband wireless communication systems. Two alternative implementations of multi-rate cascade architectures are studied and compared with conventional single-rate continuous-time topologies, taking into account the impact of main circuit-level error mechanisms, namely: mismatch, finite dc gain and gain-bandwidth product. In all cases, closed-form design equations are derived for the nonideal in-band noise power of all ΣΔ modulators under study, providing analytical relationships between their system-level performance and the corresponding circuit-level error parameters. Theoretical predictions match simulation results, showing that the lowest performance degradation is obtained by a new kind of multi-rate hybrid ΣΔ modulator, in which the front-end (continuous-time) stage operates at a higher rate than the back-end (discrete-time) stages. As a case study, the design of a hybrid GmC/switched-capacitor fourth-order (two-stage, 4-bit) cascade ΣΔ modulator is discussed to illustrate the potential benefits of the presented approachMinisterio de Economía y Competitividad TEC2010-14825/MI

The design of optimum filters for quantizing a class of non bandlimited signals

We consider the efficient quantization of a class of non bandlimited signals, namely the class of discrete time signals that can be recovered from their decimated version. By definition, these signals are oversampled and it is reasonable to expect that we can reap the same benefits of well known efficient A/D conversion techniques. Indeed, by using appropriate multirate reconstruction schemes, we first show that we can obtain a great reduction in the quantization noise variance due to the oversampled nature of the signals. To further increase the effective quantizer resolution, noise shaping is introduced by optimizing linear time invariant (LTI) and linear periodically time varying (LPTV)M pre- and post-filters around the quantizer. Closed form expressions for the optimum filters and the minimum mean squared error are derived for each case

On chopper effects in discrete-time ΣΔ modulators

Analog-to-digital converters based on ΣΔ modulators are used in a wide variety of applications. Due to their inherent monotonous behavior, high linearity, and large dynamic range, they are often the preferred option for sensor and instrumentation. Offset and flicker noise are usual concerns for this type of applications, and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Due to its simple operation principle, the action of the chopper in the integrator is often overlooked. In this paper, we provide an analytical study of the static effects in ΣΔ modulators, which shows that the introduction of chopper is not transparent to the modulator operation and should thus be designed with care.Gobierno de España TEC-2007-68072Consejo Superior de Investigaciones Científicas 200850I21

On chopper effects in discrete-time ΣΔ modulators

Analog-to-digital converters based on ΣΔ modulators are used in a wide variety of applications. Due to their inherent monotonous behavior, high linearity, and large dynamic range, they are often the preferred option for sensor and instrumentation. Offset and flicker noise are usual concerns for this type of applications, and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Due to its simple operation principle, the action of the chopper in the integrator is often overlooked. In this paper, we provide an analytical study of the static effects in ΣΔ modulators, which shows that the introduction of chopper is not transparent to the modulator operation and should thus be designed with care.This work has been partially funded by the Spanish Government project TEC-2007-68072 and the CSIC project 200850I213.Peer reviewe