ANALYSIS OF SYNCHRONIZATION PHENOMENA IN PARALLELED BUCK CONVERTERS

This paper studies bifurcation phenomena in a paralleled system of two dc-dc buck converters. A simple current mode threshold switching rule is used for the paralleled connection and the system exhibits synchronization phenomena of periodic orbits. The synchronization phenomena are suitable for current sharing for ripple reduction and fault tolerance. As parameters vary, the synchronization phenomena are changed into various complicated phenomena including chaos. In order to simplify the analysis, we introduce simple piecewise linear model. Using the mapping procedure, we analyze bifurcation from synchronization phenomena to chaos. Presenting a simple test circuit, the typical phenomena are confirmed experimentally

An asynchronous,low-power architecture for interleaved neural stimulation, using envelope and phase information

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 122-124).This thesis describes a low-power cochlear-implant processor chip and a charge-balanced stimulation chip that together form a complete processing-and-stimulation cochlear-implant system. The processor chip uses a novel Asynchronous Interleaved Stimulation (AIS) algorithm that preserves phase and amplitude cues in its spectral input while simultaneously minimizing electrode interactions and lowering average stimulation power per electrode. The stimulator chip obviates the need for large D.C. blocking capacitors in neural implants to achieve highly precise charge-balanced stimulation, thus lowering the size and cost of the implant. Thus, this thesis suggests that significant performance, power and cost improvements in the current generation of cochlear implants may be simultaneously possible. The 16-channel ~90 square mm AIS processor chip was built in a 1.5[mu]m VLSI process and consumed 107[mu]W of power over and above that of its analog spectral processing front end, which consumed 250gtW and which has been previously described. The AIS processor was found to faithfully mimic MATLAB implementations of the AIS algorithm. Two perceptual tests of the AIS algorithm with normal-hearing listeners verified that AIS signal reconstructions enabled better melody and speech recognition in noise than traditional envelope-only vocoder simulations of cochlear-implant processing. The average firing rate of the AIS processor was found to be significantly lower than in traditional synchronous stimulators, suggesting that the AIS algorithm and processor can potentially save power and improve hearing performance in cochlear-implant users. The stimulator chip was built in a 0.7glm high-voltage VLSI process and performed dynamic current balancing followed by a shorting phase.(cont.) It achieved <6nA of average DC current error, well below the targeted safety limit of 25nA for cochlear-implant patients. On +6 and -9V rails, the power consumption of a single channel of this chip was 47[mu]W when biasing power is shared by 16 channels. It puts out a charge-balanced stimulation pulse whenever it receives an asynchronous input signal from an AIS processor encoding phase information and 7-bit amplitude information, thus making the AIS processor chip and stimulator chip fully compatible in the cochlear-implant system. The AIS algorithm and charge-balancing circuits described in this work may be useful in other nerve-stimulation prosthetics where good fidelity in input-information encoding, minimization of electrode interactions, low-power strategies for stimulation, and compact charge-balanced stimulation are also important.by Ji-Jon Sit.Ph.D

Modeling for harmonic analysis of ac offshore wind power plants

This Ph.D. dissertation presents the work carried out on the modeling, for harmonic analysis, of AC offshore wind power plants (OWPP). The studies presented in this Ph.D. thesis are oriented to two main aspects regarding the harmonic analysis of this type of power system. The first aspect is the modeling and validation of the main power components of an AC offshore wind power plant. Special emphasis is focused on the modeling of wind turbines, power transformers, submarine cables, and the interaction between them. A proposal of a wind turbine harmonic model is presented in this dissertation to represent the behavior of a wind turbine and its harmonics, up to 5 kHz. The distinctive structure of this model consists of implementing a voltage source containing both the fundamental component and the harmonics emitted by the converter. For the case of transformer and submarine cables, the frequency-dependent behavior of certain parameters is modeled for frequencies up to 5 kHz as well. The modeling of the frequency-dependent characteristics, due to skin and proximity effect, is achieved by means of Foster equivalent networks for time-domain simulations. Regarding the interaction between these power components, two complementary modeling approaches are presented. These are the Simulink®-based model and an analytical sequence network model of the passive components of the OWPP. A description of model development and parameterization is carried out for both modeling approaches considering a scenario that is defined according to a real offshore wind power plant. On the other hand, the second aspect of this Ph.D. thesis is oriented to the analysis of the issues that appear in offshore wind power plants in relation to harmonic amplification risk, compliance of grid codes in terms of harmonics and power factor, and the design of effective solutions to improve the harmonic emission of the facility. The technical solutions presented in this Ph.D. thesis cover aspects regarding modulation strategies, design of the connection filter of the grid side converter and management of the operation point of the grid side converter of wind turbines. This last by means of changing the setpoint of certain variables. As inferred, these are solutions from the perspective of the wind turbine manufacturer

An analysis of the electrical circuit of submerged-arc furnaces

Bibliography: leaves 167-174.The measurement of the electrical variables of a submerged-arc furnace is difficult owing to errors in the measurement of electrode-to-bath voltages and the difficulty in maintaining measurement connections to the hot, harsh environment of a furnace. A system is proposed which provides an accurate, reliable measurement of the electrode-to-bath voltages so that the electrical variables of the furnace can be determined. A means for measurement of the arcing conditions under each electrode has also been developed. The measurement system has been used in the examination of the conduction mechanisms occurring in a furnace and this has resulted in a significant improvement in the understanding of the operation. In addition, a method for determination of the lengths of the electrodes has been established. A problem with the measurement system is that it is necessary to make connections in a hot environment and on occasions, when a furnace eruption has occurred, the measurement leads have to be replaced. As a result, an indirect technique for determination of the resistances under each electrode has been developed and used for control of the power distribution in the furnace. The technique is based on an assumption about the relationship between the reactances in the furnace and all measurements are made on the primary side of the furnace transformers where reliable connections can be made

Energy Efficient Computing with Time-Based Digital Circuits

University of Minnesota Ph.D. dissertation. May 2019. Major: Electrical Engineering. Advisor: Chris Kim. 1 computer file (PDF); xv, 150 pages.Advancements in semiconductor technology have given the world economical, abundant, and reliable computing resources which have enabled countless breakthroughs in science, medicine, and agriculture which have improved the lives of many. Due to physics, the rate of these advancements is slowing, while the demand for the increasing computing horsepower ever grows. Novel computer architectures that leverage the foundation of conventional systems must become mainstream to continue providing the improved hardware required by engineers, scientists, and governments to innovate. This thesis provides a path forward by introducing multiple time-based computing architectures for a diverse range of applications. Simply put, time-based computing encodes the output of the computation in the time it takes to generate the result. Conventional systems encode this information in voltages across multiple signals; the performance of these systems is tightly coupled to improvements in semiconductor technology. Time-based computing elegantly uses the simplest of components from conventional systems to efficiently compute complex results. Two time-based neuromorphic computing platforms, based on a ring oscillator and a digital delay line, are described. An analog-to-digital converter is designed in the time domain using a beat frequency circuit which is used to record brain activity. A novel path planning architecture, with designs for 2D and 3D routes, is implemented in the time domain. Finally, a machine learning application using time domain inputs enables improved performance of heart rate prediction, biometric identification, and introduces a new method for using machine learning to predict temporal signal sequences. As these innovative architectures are presented, it will become clear the way forward will be increasingly enabled with time-based designs

High Frequency Devices and Circuit Modules for Biochemical Microsystems

This dissertation investigates high frequency devices and circuit modules for biochemical microsystems. These modules are designed towards replacing external bulky laboratory instruments and integrating with biochemical microsystems to generate and analyze signals in frequency and time domain. The first is a charge pump circuit with modified triple well diodes, which is used as an on-chip power supply. The second is an on-chip pulse generation circuit to generate high voltage short pulses. It includes a pulse-forming-line (PFL) based pulse generation circuit, a Marx generator and a Blumlein generator. The third is a six-port circuit based on four quadrature hybrids with 2.0~6.0 GHz operating frequency tuning range for analyzing signals in frequency domain on-chip. The fourth is a high-speed sample-and-hold circuit (SHC) with a 13.3 Gs/s sampling rate and ~11.5 GHz input bandwidth for analyzing signals in time domain on-chip. The fifth is a novel electron spin resonance (ESR) spectroscopy with high-sensitivity and wide frequency tuning range

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

Assessment of US industry's technology trends and new technology requirements

The utility and effectiveness of a novel approach (the Applications Development, or AD approach), intended to augment the efficiency of NASA's technology utilization (TU) through dissemination of NASA technologies and joint technology development efforts with U.S. industry is tested. The innovative AD approach consists of the following key elements: selection of NASA technologies appearing to have leading edge attributes; interaction with NASA researchers to assess the characteristics and quality of each selected technology; identification of industry's needs in the selected technology areas; structuring the selected technologies in terms of specifications and standards familiar to industry (industrial Spec. Sheets); identification and assessment of industry's interest in the specific selected NASA technologies, utilizing the greatly facilitated communication made possible by the availability of the industrial Spec. Sheets; and matching selected NASA technologies with the needs of selected industries

Optical flow switched networks

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Includes bibliographical references (p. 253-279).In the four decades since optical fiber was introduced as a communications medium, optical networking has revolutionized the telecommunications landscape. It has enabled the Internet as we know it today, and is central to the realization of Network-Centric Warfare in the defense world. Sustained exponential growth in communications bandwidth demand, however, is requiring that the nexus of innovation in optical networking continue, in order to ensure cost-effective communications in the future. In this thesis, we present Optical Flow Switching (OFS) as a key enabler of scalable future optical networks. The general idea behind OFS-agile, end-to-end, all-optical connections-is decades old, if not as old as the field of optical networking itself. However, owing to the absence of an application for it, OFS remained an underdeveloped idea-bereft of how it could be implemented, how well it would perform, and how much it would cost relative to other architectures. The contributions of this thesis are in providing partial answers to these three broad questions. With respect to implementation, we address the physical layer design of OFS in the metro-area and access, and develop sensible scheduling algorithms for OFS communication. Our performance study comprises a comparative capacity analysis for the wide-area, as well as an analytical approximation of the throughput-delay tradeoff offered by OFS for inter-MAN communication. Lastly, with regard to the economics of OFS, we employ an approximate capital expenditure model, which enables a throughput-cost comparison of OFS with other prominent candidate architectures. Our conclusions point to the fact that OFS offers significant advantage over other architectures in economic scalability.(cont.) In particular, for sufficiently heavy traffic, OFS handles large transactions at far lower cost than other optical network architectures. In light of the increasing importance of large transactions in both commercial and defense networks, we conclude that OFS may be crucial to the future viability of optical networking.by Guy E. Weichenberg.Ph.D