An earthquake response spectrum method for linear light secondary substructures

YesEarthquake response spectrum is the most popular tool in the seismic analysis and design of structures. In the case of combined primary-secondary (P-S) systems, the response of the supporting P substructure is generally evaluated without considering the S substructure, which in turn is only required to bear displacements and/or forces imposed by the P substructure (¿cascade¿ approach). In doing so, however, dynamic interaction between the P and S components is neglected, and the seismic-induced response of the S substructure may be heavily underestimated or overestimated. In this paper, a novel CQC (Complete Quadratic Combination) rule is proposed for the seismic response of linear light S substructures attached to linear P substructures. The proposed technique overcomes the drawbacks of the cascade approach by including the effects of dynamic interaction and different damping in the substructures directly in the cross-correlation coefficients. The computational effort is reduced by using the eigenproperties of the decoupled substructures and only one earthquake response spectrum for a reference value of the damping ratio

Response of beams resting on viscoelastically damped foundation to moving oscillators

The response of beams resting on viscoelastically damped foundation under moving SDoF oscillators is scrutinized through a novel state-space formulation, in which a number of internal variables is introduced with the aim of representing the frequency-dependent behaviour of the viscoelastic foundation. A suitable single-step scheme is provided for the numerical integration of the equations of motion, and the Dimensional Analysis is applied in order to define the dimensionless combinations of the design parameters that rule the responses of beam and moving oscillator. The effects of boundary conditions, span length and number of modes of the beam, along with those of the mechanical properties of oscillator and foundation, are investigated in a new dimensionless form, and some interesting trends are highlighted. The inaccuracy associated with the use of effective values of stiffness and damping for the viscoelastic foundation, as usual in the present state-of-practice, is also quantified

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

Time-Domain/Digital Frequency Synchronized Hysteresis Based Fully Integrated Voltage Regulator

abstract: Power management integrated circuit (PMIC) design is a key module in almost all electronics around us such as Phones, Tablets, Computers, Laptop, Electric vehicles, etc. The on-chip loads such as microprocessors cores, memories, Analog/RF, etc. requires multiple supply voltage domains. Providing these supply voltages from off-chip voltage regulators will increase the overall system cost and limits the performance due to the board and package parasitics. Therefore, an on-chip fully integrated voltage regulator (FIVR) is required. The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking. The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201