Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

In this paper, the hardware acceleration of a tone-mapping algorithm for High-Dynamic-Range image processing is presented. Starting from the C++ source code, High-Level Synthesis has been performed using Xilinx SDSoC for a Xilinx Zynq SoC device. After an initial code optimization to improve the memory access bottleneck, SDSoC pragmas have been introduced to boost system performance through an increased parallelism. Preliminary results have shown significant reductions in the execution time and the energy consumption compared to the conventional software implementation

Aprendizaje en el funcionamiento de la herramienta SDSoC de Xilinx para diseños basados en dispositivos SoC

En este TFG, se expondrán los distintos pasos a seguir para crear proyectos que se puedan implementar en un SoC haciendo uso de la herramienta SDSoC. En ellos, se hará uso del particionado HW/SW para poder acelerar el algoritmo que se esté desarrollando. Para comprobar el gran potencial de esta herramienta y poder ilustrar los distintos pasos que se deben seguir para poder llegar a un proyecto que se pueda implementar. Se usará como ejemplo el algoritmo PCA aplicado a un set de imágenes cargadas en memoria. Para ello, se usarán librerías de OpenCV y un Sistema Operativo.This Final Project addresses the different steps to implement a whole approach under a System on Chip (SoC) device. The use of SDSoC tool provided by Xilinx allows an easy way to make a HW-SW partition in order to speed up the algorithm to be implemented. To validate the use for the speed-up of a user case, the Principal Component Analysis (PCA) technique is implemented for a Zynq device with SDSoC. An approach based on OpenCV libraries and a Linux Operating System is done to validate the benefits of this tool.Grado en Ingeniería en Tecnologías de Telecomunicació

Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC

Nowadays, new heterogeneous system technologies are flooding the market: through the past years, it is possible to observe the move from single CPUs to multi-core devices featuring CPUs, GPUs and large FPGAs, such as Xilinx Zynq-7000 or Zynq UltraScale+ MPSoC architectures. In this context, providing developers with transparent deployment capabilities to efficiently execute different applications on such complex devices is important. In this paper, a design flow that combines, on one side, PREESM, a dataflow-based prototyping framework and, on the other side, Xilinx SDSoC, an HLS-based framework to automatically generate and manage hardware accelerators, is presented. This integration leverages the automatic, static task scheduling obtained from PREESM with asynchronous invocations that trigger the parallel execution of multiple hardware accelerators from some of their associated sequential software threads. An image processing application is used as a proof of concept, showing the interoperability possibilities of both tools, the level of design automation achieved and, for the resulting computing architecture, the good performance scalability according to the number of accelerators and sw threads