Energy efficient HPC network topologies with on/off links

Producción CientíficaEnergy efficiency is a must in today HPC systems. To achieve this goal, a holistic design based on the use of power-aware components should be performed. One of the key components of an HPC system is the high-speed interconnect. In this paper, we compare and evaluate several design options for the interconnection network of an HPC system, including torus, fat-trees and dragonflies. State of the art low power modes are also used in the interconnection networks. The paper does not only consider energy efficiency at the interconnection network level but also at the system as a whole. The analysis is performed by using a simple yet realistic power model of the system. The model has been adjusted using actual power consumption values measured on a real system. Using this model, realistic multi-job trace-based workloads have been used, obtaining the execution time and energy consumed. The results are presented to ease choosing a system, depending on which parameter, performance or energy consumption, receives the most importance.Ministerio de Economía, Industria y Competitividad (projects PID2019-105903RB-100 and PID2021-123627OB)Junta de Comunidades de Castilla-La Mancha (project SBPLY/21/180501/ 000248

Open FPGA-based development platform for fuzzy systems with applications to communications

Soft computing techniques are gaining momentum as tools for network traffic modeling, analysis and control. Efficient hardware implementations of these techniques that can achieve real-time operation in high-speed communications equipment is however an open problem. This paper describes a platform for the development of fuzzy systems with applications to communications systems, namely network traffic analysis and control. An FPGA development board with PCI interface is employed to support an open platform that comprises open CAD tools as well as IP cores. For the development process, we set up a methodology and a CAD tools chain that cover from initial specification in a high-level language to implementation on FPGA devices. PCI compatible fuzzy inference modules are implemented as SoPC based on the open WISHBONE interconnection architecture. We outline results from the design and implementation of fuzzy analyzers and regulators for network traffic. These systems are shown to satisfy operational and architectural requirements of current and future high-performance routing equipment.Ministerio de Educación y Ciencia TEC2005-04359/MICJunta de Andalucía TIC2006-63

An Efficient Medium Access Control Strategy for High Speed WDM Multiaccess Networks

A medium access control (MAC) strategy that accounts for the limited tunability of present-day lasers and filters and yet supports a large total number of wavelengths in the network is proposed. Full interconnectivity, contention-free access and a high value of concurrency are achieved by dividing the network into disjunct subnetworks on a wavelength basis and by reconfiguring these subnetworks on a time basis. Each subnetwork allows for simplified access to be implemented with fast tunable transceivers each assessing only a moderate number of wavelengths. A performance analysis shows that this concept is most efficient when applied to a high-level broadband interconnection metropolitan area network (MAN

Cycle-accurate evaluation of reconfigurable photonic networks-on-chip

There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores. Photonic Networks-on-Chip (NoCs) have been suggested as a viable route to relieve the off- and on-chip interconnection bottleneck. Low-loss integrated optical waveguides can transport very high-speed data signals over longer distances as compared to on-chip electrical signaling. In addition, with the development of silicon microrings, photonic switches can be integrated to route signals in a data-transparent way. Although several photonic NoC proposals exist, their use is often limited to the communication of large data messages due to a relatively long set-up time of the photonic channels. In this work, we evaluate a reconfigurable photonic NoC in which the topology is adapted automatically (on a microsecond scale) to the evolving traffic situation by use of silicon microrings. To evaluate this system's performance, the proposed architecture has been implemented in a detailed full-system cycle-accurate simulator which is capable of generating realistic workloads and traffic patterns. In addition, a model was developed to estimate the power consumption of the full interconnection network which was compared with other photonic and electrical NoC solutions. We find that our proposed network architecture significantly lowers the average memory access latency (35% reduction) while only generating a modest increase in power consumption (20%), compared to a conventional concentrated mesh electrical signaling approach. When comparing our solution to high-speed circuit-switched photonic NoCs, long photonic channel set-up times can be tolerated which makes our approach directly applicable to current shared-memory CMPs

Multilayer optical learning networks

A new approach to learning in a multilayer optical neural network based on holographically interconnected nonlinear devices is presented. The proposed network can learn the interconnections that form a distributed representation of a desired pattern transformation operation. The interconnections are formed in an adaptive and self-aligning fashioias volume holographic gratings in photorefractive crystals. Parallel arrays of globally space-integrated inner products diffracted by the interconnecting hologram illuminate arrays of nonlinear Fabry-Perot etalons for fast thresholding of the transformed patterns. A phase conjugated reference wave interferes with a backward propagating error signal to form holographic interference patterns which are time integrated in the volume of a photorefractive crystal to modify slowly and learn the appropriate self-aligning interconnections. This multilayer system performs an approximate implementation of the backpropagation learning procedure in a massively parallel high-speed nonlinear optical network

Full duplex switched ethernet for next generation "1553B" -based applications

Over the last thirty years, the MIL-STD 1553B data bus has been used in many embedded systems, like aircrafts, ships, missiles and satellites. However, the increasing number and complexity of interconnected subsystems lead to emerging needs for more communication bandwidth. Therefore, a new interconnection system is needed to overcome the limitations of the MIL-STD 1553B data bus. Among several high speed networks, Full Duplex Switched Ethernet is put forward here as an attractive candidate to replace the MIL-STD 1553B data bus. However, the key argument against Switched Ethernet lies in its non-deterministic behavior that makes it inadequate to deliver hard timeconstrained communications. Hence, our primary objective in this paper is to achieve an accepted QoS level offered by Switched Ethernet, to support diverse "1553B"-based applications requirements. We evaluate the performance of traffic shaping techniques on Full Duplex Switched Ethernet with an adequate choice of service strategy in the switch, to guarantee the real-time constraints required by these specific 1553B-based applications. An analytic study is conducted, using the Network Calculus formalism, to evaluate the deterministic guarantees offered by our approach. Theoretical analysis are then investigated in the case of a realistic "1553B"-based application extracted from a real military aircraft network. The results herein show the ability of profiled Full Duplex Switched Ethernet to satisfy 1553B-like real-time constraints

Internet Peering as a Network of Relations

We apply results from recent theoretical work on networks of relations to analyze optimal peering strategies for asymmetric ISPs. It is shown that - from a network of relations perspective – ISPs’ asymmetry in bilateral peering agreements need not be a problem, since when these form a closed network, asymmetries are pooled and information transmission is faster. Both these effects reduce the incentives for opportunism in general, and interconnection quality degradation in particular. We also explain why bilateral monetary transfers between asymmetric ISPs (Bilateral Paid Peering), though potentially good for bilateral peering, may have rather negative effects on the sustainability of the overall peering network