Projected Range Dependent Tunneling Current of Asymmetric Double Gate MOSFET

This study is to analyze the changes of tunneling current according to projected range, a variable of Gaussian function of channel doping function of Asymmetric Double Gate; ADG MOSFET. In MOSFET with channel length below 10 nm, tunneling current occupies a large percentage among off-currents. The increase of tunneling current has a large effect on the characteristics of subthreshold such as threshold voltage movement and the decline of subthreshold swing value, so the accurate analysis of this is being required. To analyze this, potential distribution of series form was obtained using Gaussian distribution function, and using this hermeneutic potential distribution, thermionic emission current and tunneling current making up off-current were obtained. At this point, the effect that the changes of projected range, a variable of Gaussian distribution function, have on the ratio of tunneling current among off-currents was analyzed. As a result, the smaller projected range was, the lower the ratio of tunneling current was. When projected range increased, tunneling current increased largely. Also, it was observed that the value of projected range which the ratio of tunneling current increased changed according to maximum channel doping value, channel length, and channel width

Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric Double Gate MOSFET

This study is to analyze threshold voltage roll-off according to structural parameters of sub-10 nm asymmetric double gate MOSFET. In case of sub-10nm channel length, because of short channel effects resulting from the rapid increase of tunneling current, even asymmetric double gate (DG) MOSFET, which has been developed for reducing short channel effects, will increase threshold voltage roll-off, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Especially, since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top/bottom oxide thickness will affect the threshold voltage roll-off. To analyze this, thermal emission current and tunneling current model have been calculated, and threshold voltage roll-off in accordance with the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off, in particular, is generated more greatly according to silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltag

SPICE model of drain induced barrier lowering in sub-10 nm junctionless cylindrical surrounding gate MOSFET

We propose a SPICE Drain Induced Barrier Lowering (DIBL) model for sub-10 nm Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs. The DIBL shows the proportionl relation to the -3 power of the channel length Lg and the 2 power of silicon thickness in MOSFET having a rectangular channel, but this relation cannot be used in cylindrical channel because of the difference in channel structure. The subthreshold currents, including the tunneling current from the WKB (Wentzel-Kramers-Brillouin) approximation as well as the diffusion-drift current, are used in the model. The constant current method is used to define the threshold voltage as the gate voltage at a constant current, (2πR/Lg)10-7 A for channel length and channel radius R. The central potential of the JLCSG MOSFET is determined by the Poisson equation. As a result, it can be seen that the DIBL of the JLCSG MOSFET is proportional to the –2.76 power of the channel length, to the 1.76 power of the channel radius, and linearly to the oxide film thickness. At this time, we observe that the SPICE parameter, the static feedback coefficient, has a value less than 1 1, and this model can be used to analyze the DIBL of the JLCSG MOSFET

Investigation on Performance Metrics of Nanoscale Multigate MOSFETs towards RF and IC Applications

Silicon-on-Insulator (SOI) MOSFETs have been the primary precursor for the CMOS technology since last few decades offering superior device performance in terms of package density, speed, and reduced second order harmonics. Recent trends of investigation have stimulated the interest in Fully Depleted (FD) SOI MOSFET because of their remarkable scalability efficiency. However, some serious issues like short channel effects (SCEs) viz drain induced barrier lowering (DIBL), Vth roll-off, subthreshold slope (SS), and hot carrier effects (HCEs) are observed in nanoscale regime. Numerous advanced structures with various engineering concepts have been addressed to reduce the above mentioned SCEs in SOI platform. Among them strain engineering, high-k gate dielectric with metal gate technology (HKMG), and non-classical multigate technologies are most popular models for enhancement in carrier mobility, suppression of gate leakage current, and better immunization to SCEs. In this thesis, the performance of various emerging device designs are analyzed in nanoscale with 2-D modeling as well as through calibrated TCAD simulation. These attempts are made to reduce certain limitations of nanoscale design and to provide a significant contribution in terms of improved performances of the miniaturized devices. Various MOS parameters like gate work function (_m), channel length (L), channel thickness (tSi), and gate oxide thickness (tox) are optimized for both FD-SOI and Multiple gate technology. As the semiconductor industries migrate towards multigate technology for system-on-chip (SoC), system-in-package (SiP), and internet-of-things (IoT) applications, an appropriate examination of the advanced multiple gate MOFETs is required for the analog/RF application keeping reliability issue in mind. Various non-classical device structures like gate stack engineering and halo doping in the channel are extensively studied for analog/RF applications in double gate (DG) platform. A unique attempt has been made for detailed analysis of the state-of-the-art 3-D FinFET on dependency of process variability. The 3-D architecture is branched as Planar or Trigate or FinFET according to the aspect ratio (WFin=HFin). The evaluation of zero temperature coefficient (ZTC) or temperature inflection point (TCP) is one of the key investigation of the thesis for optimal device operation and reliability. The sensitivity of DG-MOSFET and FinFET performances have been addressed towards a wide range of temperature variations, and the ZTC points are identified for both the architectures. From the presented outcomes of this work, some ideas have also been left for the researchers for design of optimum and reliable device architectures to meet the requirements of high performance (HP) and/or low standby power (LSTP) applications

GIDL characteristics on Si1-xGex pFinFET for Low Power Transistors

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 신형철.This dissertation presents an investigation of Gate-Induced-Drain-Leakage (GIDL) current in SiliconGermanium (SiGe) p-type FinFET for low power transistors and proposes the guidelines to reduce GIDL current. First, the main mechanism of GIDL current in FinFET was thoroughly investigated because conventional GIDL current is unexpected event in FinFET. Therefore, GIDL current in FinFET is analyzed by comparing that in MOSFET which has the same device specification as the FinFET. Second, the effects of Ge fraction and its distribution in internal fin on GIDL current were analyzed considering actually manufactured fin in SiGe FinFET. Third, the analysis of GIDL current by the device specifications and doping profile in drain region was presented. As a result, guidelines are presented considering the results above. The main mechanism and the characteristics of GIDL current in FinFET which are investigated in this dissertation would be and index to improve the characteristics of manufactured SiGe FinFET.Chapter 1. Introduction 1 1.1. Multigate MOSFET 1 1.2. SiliconGermanium (SiGe) characteristics 4 1.3. Scope and Organization 7 Chapter 2. Gate-Induced-Drain-leakage current in FinFET 8 2.1. Introduction 8 2.2. Modeling of GIDL current 12 2.3. Comparison of GIDL between MOSFET and FinFET 16 2.4. Summary 28 Chapter 3. Effects of device specifications on GIDL 29 3.1. Introduction 29 3.2. Effects of Ge fraction in Si1-xGex pFinFET on GIDL 30 3.3. Effects of manufacturing process conditions on GIDL 41 3.4. Effects of doping profile on GIDL 49 3.5. Junction depth under the drain region 58 3.6. Summary 63 Chapter 4. Optimization of Si1-xGex pFinFET for low-power transistor 64 Chapter 5. Conclusion 68 Appendix A. Leakage current by strain engineering 70 A.1. Introduction 70 A.2. Effect of interface traps on leakage current 72 A.3. Effect of band-gap on leakage current 75 A.4. Conclusion 77 Abstract in Korean 90Docto