Dynamic Partial Reconfiguration for Dependable Systems

Moore’s law has served as goal and motivation for consumer electronics manufacturers in the last decades. The results in terms of processing power increase in the consumer electronics devices have been mainly achieved due to cost reduction and technology shrinking. However, reducing physical geometries mainly affects the electronic devices’ dependability, making them more sensitive to soft-errors like Single Event Transient (SET) of Single Event Upset (SEU) and hard (permanent) faults, e.g. due to aging effects. Accordingly, safety critical systems often rely on the adoption of old technology nodes, even if they introduce longer design time w.r.t. consumer electronics. In fact, functional safety requirements are increasingly pushing industry in developing innovative methodologies to design high-dependable systems with the required diagnostic coverage. On the other hand commercial off-the-shelf (COTS) devices adoption began to be considered for safety-related systems due to real-time requirements, the need for the implementation of computationally hungry algorithms and lower design costs. In this field FPGA market share is constantly increased, thanks to their flexibility and low non-recurrent engineering costs, making them suitable for a set of safety critical applications with low production volumes. The works presented in this thesis tries to face new dependability issues in modern reconfigurable systems, exploiting their special features to take proper counteractions with low impacton performances, namely Dynamic Partial Reconfiguration

Embedded electronic systems driven by run-time reconfigurable hardware

Abstract This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.Resumen Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.Resum Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria

Characterization of Interconnection Delays in FPGAS Due to Single Event Upsets and Mitigation

RÉSUMÉ L’utilisation incessante de composants électroniques à géométrie toujours plus faible a engendré de nouveaux défis au fil des ans. Par exemple, des semi-conducteurs à mémoire et à microprocesseur plus avancés sont utilisés dans les systèmes avioniques qui présentent une susceptibilité importante aux phénomènes de rayonnement cosmique. L'une des principales implications des rayons cosmiques, observée principalement dans les satellites en orbite, est l'effet d'événements singuliers (SEE). Le rayonnement atmosphérique suscite plusieurs préoccupations concernant la sécurité et la fiabilité de l'équipement avionique, en particulier pour les systèmes qui impliquent des réseaux de portes programmables (FPGA). Les FPGA à base de cellules de mémoire statique (SRAM) présentent une solution attrayante pour mettre en oeuvre des systèmes complexes dans le domaine de l’avionique. Les expériences de rayonnement réalisées sur les FPGA ont dévoilé la vulnérabilité de ces dispositifs contre un type particulier de SEE, à savoir, les événements singuliers de changement d’état (SEU). Un SEU est considérée comme le changement de l'état d'un élément bistable (c'est-à-dire, un bit-flip) dû à l'effet d'un ion, d'un proton ou d’un neutron énergétique. Cet effet est non destructif et peut être corrigé en réécrivant la partie de la SRAM affectée. Les changements de délai (DC) potentiels dus aux SEU affectant la mémoire de configuration de routage ont été récemment confirmés. Un des objectifs de cette thèse consiste à caractériser plus précisément les DC dans les FPGA causés par les SEU. Les DC observés expérimentalement sont présentés et la modélisation au niveau circuit de ces DC est proposée. Les circuits impliqués dans la propagation du délai sont validés en effectuant une modélisation précise des blocs internes à l'intérieur du FPGA et en exécutant des simulations. Les résultats montrent l’origine des DC qui sont en accord avec les mesures expérimentales de délais. Les modèles proposés au niveau circuit sont, aux meilleures de notre connaissance, le premier travail qui confirme et explique les délais combinatoires dans les FPGA. La conception d'un circuit moniteur de délai pour la détection des DC a été faite dans la deuxième partie de cette thèse. Ce moniteur permet de détecter un changement de délai sur les sections critiques du circuit et de prévenir les pannes de synchronisation engendrées par les SEU sans utiliser la redondance modulaire triple (TMR).----------ABSTRACT The unrelenting demand for electronic components with ever diminishing feature size have emerged new challenges over the years. Among them, more advanced memory and microprocessor semiconductors are being used in avionic systems that exhibit a substantial susceptibility to cosmic radiation phenomena. One of the main implications of cosmic rays, which was primarily observed in orbiting satellites, is single-event effect (SEE). Atmospheric radiation causes several concerns regarding the safety and reliability of avionics equipment, particularly for systems that involve field programmable gate arrays (FPGA). SRAM-based FPGAs, as an attractive solution to implement systems in aeronautic sector, are very susceptible to SEEs in particular Single Event Upset (SEU). An SEU is considered as the change of the state of a bistable element (i.e., bit-flip) due to the effect of an energetic ion or proton. This effect is non-destructive and may be fixed by rewriting the affected part. Sensitivity evaluation of SRAM-based FPGAs to a physical impact such as potential delay changes (DC) has not been addressed thus far in the literature. DCs induced by SEU can affect the functionality of the logic circuits by disturbing the race condition on critical paths. The objective of this thesis is toward the characterization of DCs in SRAM-based FPGAs due to transient ionizing radiation. The DCs observed experimentally are presented and the circuit-level modeling of those DCs is proposed. Circuits involved in delay propagation are reverse-engineered by performing precise modeling of internal blocks inside the FPGA and executing simulations. The results show the root cause of DCs that are in good agreement with experimental delay measurements. The proposed circuit level models are, to the best of our knowledge, the first work on modeling of combinational delays in FPGAs.In addition, the design of a delay monitor circuit for DC detection is investigated in the second part of this thesis. This monitor allowed to show experimentally cumulative DCs on interconnects in FPGA. To this end, by avoiding the use of triple modular redundancy (TMR), a mitigation technique for DCs is proposed and the system downtime is minimized. A method is also proposed to decrease the clock frequency after DC detection without interrupting the process

Plataforma para testes e qualificação de dispositivos reconfiguráveis e sistemas em chip, submetidos aos efeitos combinados da interferência eletromagnética e da radiação ionizante

Tese (doutorado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia Elétrica, Florianópolis, 2015.Este trabalho investiga os efeitos combinados da radiação e interferência eletromagnética em sistemas embarcados críticos baseados em dispositivos reconfiguráveis (FPGAs). Os efeitos investigados podem ser resultantes de interferência eletromagnética, conduzida ou radiada, ou através de radiação ionizante, por acúmulo de dose total (Total Ionizing Dose, ou TID) ou por efeitos de evento único, denominados de Single Event Effects (SEE). Dispositivos do tipo FPGA têm sido cada vez mais utilizados em sistemas críticos, devido a sua versatilidade, desempenho e robustez. O presente estudo contribui para a caracterização e qualificação de dispositivos FPGAs quando em funcionamento em ambientes ruidosos. O cenário descrito motivou a proposta deste trabalho, que contempla três objetivos principais: (1) O projeto, desenvolvimento e validação de uma plataforma para ensaios combinados de radiação e de interferência eletromagnética (conduzida e radiada) usando como referência o conjunto de normas IEC 62.132. (2) Desenvolver uma metodologia para qualificar sistemas em chip (SoCs) implementados em FPGA levando-se em conta os efeitos combinados da radiação (TID e SEE) e da interferência eletromagnética (EMI radiada e conduzida); (3) Demonstrar a utilização integrada da metodologia e plataforma para qualificação destes dispositivos e os sistemas em chip utilizados no que diz respeito à dose de radiação, tempo de atraso entre entrada e saída, tensão mínima de funcionamento, consumo de corrente dinâmico, nível de campo eletromagnético máximo suportado antes da falha, a faixa de frequências em que os dispositivos apresentaram falhas com outros valores de campo e a sensibilidade à Single Event Upsets (SEU) tendo seus efeitos combinados com TID e EMI. Cabe salientar que estas plataformas de testes deste nível e para este propósito não foram encontradas na literatura nem no Brasil nem no exterior, nos motivando ainda mais a pesquisa e o desenvolvimento pela sua originalidade e grande utilidade para projetos que envolvem sistemas em chip utilizando FPGAs quando submetidos à radiação e à EMI. Principalmente quando aplicado a sistemas embarcados para aplicações críticas. A plataforma desenvolvida é baseada em três placas específicas e complementares em duas versões. A primeira é dedicada para ensaios com radiação ionizante, e pode ser utilizada em uma câmara aceleradora de partículas ou em uma Gamma Cell (para exposição a raios gama) ou ainda em equipamentos de raios X. A segunda placa é dedicada para o teste de imunidade à EMI radiada utilizando uma Giga-hertz Transverse Electromagnetic Cell (GTEM Cell) de acordo com a norma IEC 62.132-2 e a terceira é uma placa de injeção de EMI conduzido pelas linhas de alimentação do circuito, e usou como referência a norma IEC 61.000-4-29. Com a plataforma e metodologia apresentadas neste trabalho foi possível comprovar que quanto maior a dose de radiação recebida, mais susceptível o dispositivo fica quando exposto à EMI, aumentando em pelo menos 30% a quantidade de falhas, em até 230% o tempo de atraso entre entrada e saída e em até 19% o consumo de corrente dinâmico do dispositivo. Assim como quanto maior a dose de radiação sofrida, maior será a sensibilidade à SEU. Com os limites de operação apresentados para os FPGAs em teste, o projetista pode decidir se o dispositivo está ou não qualificado para o seu uso em determinada aplicação.Abstract : The combined effects of radiation and electromagnetic interference in reconfigurable devices (FPGAs) are explored in this work. The investigated effects can originate from radiated or conducted electromagnetic interference, through ionizing radiation, by accumulation of total dose (Total Ionizing Dose TID) or by Single Event Effects also known as SEE. Since FPGA devices have been increasingly used in critical systems, due to their versatility, performance and robustness, this study contributes to the characterization and qualification of FPGAs devices when operating in noisy environments. The described scenario resulted in a proposal with three main objectives: (1) The design, development and validation of a platform for combined tests for radiation and electromagnetic interference (conducted and radiated) with reference to IEC 62.132 standards. (2) Development of a methodology to qualify systems on chip (SoC) implemented in FPGA taking into account the combined effects of radiation (TID and SEE) and electromagnetic interference (EMI radiated and conduced); (3) Demonstrate the combined use of the methodology and platform for qualifications of these devices and SoC used with respect to radiation dose, time delay between input and output, minimum operating voltage, the dynamic power consumption, electromagnetic field level supported before failure, the frequency range in which the devices had failures with other field values and sensitivity to Single Event Upsets (SEU) with TID and EMI combined effects. It should be emphasized that these test platforms, at this level and for this purpose have not been found in the literature either in Brazil or in other countries, motivating this research and development for its originality and use in projects involving systems on chip on FPGAs when exposed to radiation and EMI. Especially when applied to embedded systems for critical applications. The developed platform is based on three specific and complementary boards in two versions. The first one is dedicated to radiation immunity test according to the IEC 62132-2 standard, and can be used in a particle accelerator chamber (e.g. protons) Gamma Cell (for gamma rays exposure) or in X ray equipment s. The second board is dedicated to radiated noise immunity testing in a Giga- Hertz Transverse Electromagnetic Cell (GTEM Cell) referenced by the IEC 62.132-2 standard. The third one is a board for conducted EMI injection by the circuit supply lines referenced by the IEC 61.000-4-29 standard. With the platform and methodology presented in this work it was possible to prove that the higher radiation dose received, the more susceptible when exposed to EMI the device is, increasing by at least 30 % the number of failures, up to 230 % the time delay between input and output and up to 19 % dynamic current consuming of the device. As well as the higher the radiation dose suffered, the more sensitivity to SEU is. With operating limits presented for FPGAs under test, the designer can decide if the device is qualified or not for use in a particular application

Analysis of SEU Effects in Partially Reconfigurable SoPCs

Sterpone L, Margaglia F, Köster M, Hagemeyer J, Porrmann M. Analysis of SEU Effects in Partially Reconfigurable SoPCs. In: European Space Agency, Jet Propulsion Laboratory, USA. National Aeronautics and Space Administration, The University of Edinburgh. National Aeronautics and Space Administration, eds. Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011). Piscataway, NJ: IEEE; 2011: 129-136.Systems on Programmable Chips (SoPCs) are receiving an increasing interest from various application domains. Safety critical missions, driven by space and avionics applications, are especially attracted in using SoPCs due to low non-recurring engineering costs, reconfigurability and the large number of logic resources they provide. The capability of partial reconfiguration has recently become a promising approach to enhance the flexibility of a given system and to adapt and customize to different requirements. However, Single Event Upsets (SEUs) induced by radiation environment where space and avionics system operate, have a critical and catastrophic effect in these devices. In this paper, we propose a novel algorithm, which is able to identify critical SEUs corrupting the functionality of a SoPC using dynamic and partial reconfiguration. The algorithm is based on an analyzer able to interact with the dynamic system components containing partial reconfiguration modules, the communication infrastructure and the static region. Efficient critical SEUs estimation depends not only on the independent component mapping but also on the routing interaction between reconfigurable modules placed in different feasible positions. The analysis algorithm has been proven on a partially reconfigurable platform using different applications, besides it has been validated by means of fault injection campaigns of SEUs into SoPC's configuration memory. The experimental results demonstrated the effectiveness of the developed algorithm. Fault injection results have been accurately investigated and commented