A Recofigurable Tri-Band Interconnect for Future Network-On-Chip

The scaling of CMOS feature sizes has yielded the capability of integrating heterogeneous intellectual properties (IPs) like graphics processing units (GPUs), digital signal processors (DSPs) and central processing units (CPUs) on a single die. The collection of multiple IPs on a single die presents a problem of reliable communication due to congestion. The infrastructure that facilitates and manages communication among IPs is referred to as a network-on-chip (NoC). Its ultimate goal should be low latency with negligible power and area consumption. Unfortunately, as CMOS feature sizes have been scaling smaller, this has exacerbated latency and signal degradation due to increasing on-chip channel resistance. Furthermore, contemporary interfaces use baseband-only signaling and have critical limitations like exponential energy consumption, limited bandwidth and non-reconfigurable data access.;In this work, we propose an energy efficient tri-band (baseband + 2 RF bands) signaling interface that is capable of simultaneous bi-directional communication and reconfigurable data access. Additionally, communication is accomplished through a shared transmission line which reduces the overall number of global interconnections. As a result, this reduces area consumption and mitigates interconnection complexity. The primary signicance of this interconnect configuration compared to contemporary designs is an increase of bandwidth and energy efficiency.;The interconnect design is composed of a baseband transceiver and two RF (10Ghz and 20GHz) transceivers. The RF transceivers utilize amplitude-shift keying (ASK) modulation scheme. ASK modulation allows ease of circuit design, but most importantly it can be used for noncoherent communication, which we implemented in this system. Noncoherent ASK modulation is area conservative and power efficient since there is no longer a need for power-hungry frequency synthesizers. Moreover, noncoherent ASK demodulation accomplishes direct-down conversation through a passive self-mixer for additional power savings.;The results from our work show that a multi-band interconnect is a suitable remedy for future NoC communication that has been reaching its bandwidth limitation with baseband-only signaling. In conclusion, this work demonstrates a sustainable balance of energy efficiency and increased bandwidth for future on-chip interconnect designs

Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall

abstract: The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon. A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Engineering evaluations and studies. Volume 3: Exhibit C

High rate multiplexes asymmetry and jitter, data-dependent amplitude variations, and transition density are discussed

Investigation of the atmospheric optical communication as a part of the bridge crane control system of the radioactive waste storage

Чермалих, О. В. Дослідження атмосферного оптичного каналу зв’язку в складі системи управління мостовим краном сховища радіоактивних відходів = Investigation of the atmospheric optical communication as a part of the bridge crane control system of the radioactive waste storage / О. В. Чермалих, Д. Д. Мугенов // Shipbuilding & Marine Infrastructure. – 2020. – № 2 (14). – С. 46–57.Анотація. У статті розглянуто структуру атмосферного оптичного каналу зв’язку системи управління електроприводами мостового крана сховища радіоактивних відходів. Критерієм якості атмосферного оптичного каналу зв’язку є коефіцієнт бітових помилок: чим нижчий коефіцієнт бітових помилок, тим надійніша передача даних. Розглянуто вплив факторів, що збільшують коефіцієнт бітових помилок, таких, як: не безкінечно вузька діаграма спрямованості випромінювача передавача, шум, іонізуюче випромінювання, природна деградація емісії лазера передавача, ослаблення випромінювання в атмосфері. Переміщення мосту крана в дальнє положення призводить до збільшення коефіцієнту бітових помилок оптичного каналу зв’язку. Тому зростає імовірність недостовірної передачі команд із пульта управління на контролер керування електроприводами. В умовах роботи з потенційно небезпечними вантажами (блоки радіоактивних відходів) помилка може призвести до аварійної ситуації. Метою роботи є дослідження факторів, що сприяють збільшенню коефіцієнта бітових помилок, та розробка демодулятора для підвищення якості атмосферного оптичного зв’язку за допомогою програмного зменшення коефіцієнта бітових помилок. Методика. Для досягнення поставленої мети вважається доцільним використання штучних нейронних мереж у структурі демодулятора. Модель атмосферного оптичного зв’язку побудована в Matlab Simulink. Проведено синтез, навчання та тестування штучних нейронних мереж. Результати. Отримано і досліджено моделі атмосферного оптичного зв’язку із традиційним та нейромережевими демодуляторами. Виявлено, що застосування штучної нейронної мережі прямого поширення із затримками входу дає змогу знизити коефіцієнт бітових помилок на усьому дослідженому діапазоні відношення сигнал/шум, у той час як ймовірнісна мережа демонструє найнижчий коефіцієнт бітових помилок лише в діапазоні від 0 до 0,7 дБ. Запропоновано вдосконалення конструкції демодулятора приймача, що дає змогу застосовувати атмосферний оптичний канал керування електроприводами мостового крану в умовах підвищеної радіації. Наукова новизна. Для покращення якості каналу управління електроприводом мостового крана були досліджені демодулятори на основі дев’яти типів штучних нейронних мереж. У цій статті розглянуто два типи нейромережевих демодуляторів, які дозволили зменшити коефіцієнт бітових помилок. Практична значимість. Запропоновано вдосконалення атмосферного оптичного каналу зв’язку системи управління електроприводами мостового крану сховища радіоактивних відходів. Розроблений нейромережевий демодулятор дає змогу використовувати оптичний канал управління в умовах підвищеної радіації.Abstract. The article considers atmospheric optical communication structure of the bridge crane electric drive control system of the radioactive waste storage. The criterion for the quality of atmospheric optical communication is bit error rate: the lower bit error rate, the more reliable the data transmission. The effect of factors that increase bit error rate, such as beam divergence, noise, ionizing radiation, natural degradation of laser emissions, attenuation of radiation in the atmosphere are considered. Moving the crane bridge to the far position leads to optical communication channel bit error rate increasing. Therefore, the probability of inaccurate transmission of commands from the control panel to the controller of electric drives increases. In the conditions of work with potentially dangerous cargoes (radioactive waste) the mistake can lead to an emergency situation. Purpose. The aim is to investigate the factors that contribute to the increase in the bit error rate and to develop demodulator to perform atmospheric optical communication quality enhancement through reducing bit error rate in a software way. Methodology. To achieve this goal, the use of artificial neural networks in the demodulator structure is considered appropriate. The atmospheric optical communication model is built in Matlab Simulink. Synthesis, training and testing of artificial neural networks were performed. Results. The atmospheric optical communication models with conventional and neural network demodulators are received. Exploration of neural networks demodulators models demonstrates that the use of a feed forward network with an input delay can reduce bit error rate over the entire range of signal-to-noise ratio. Probablistic neural network performs the lowest bit error rate in the signal-to-noise ratio range from 0 to 0.7 dB. Scientific novelty. In order to improve the quality of bridge crane electric drive control channel, demodulators based on nine types of artificial neural networks were investigated. Two neural network demodulators which allowed to reduce the bit error rate are considered in this article. The bridge crane electric drives optical control channel models with conventional and neural network demodulators are compared. Practical significance. The improvement of the bridge crane electric drives atmospheric optical control channel is proposed. The developed neural network demodulator allows the use of an optical control channel in conditions of increased radiation

High-speed and Robust Integrated Silicon Nanophotonics for On-Chip Interconnects

Optical interconnects offer advantages over electrical interconnects such as higher bandwidth, low power, reduced interconnects delay, and immunity to electro-magnetic interference and signal crosstalk. However, in order for optical interconnects to be widely adopted, the technology must be made cost effective and must be simple to implement with CMOS electronics. Silicon photonics offers a great promise due to its inexpensive material and its compatibility with the current CMOS fabrication technology. Moreover, Silicon as a platform has the ability to integrate with different types of the optical components such as photodetector, modulator, light source, and waveguide to form a photonics integrated circuit. The goal of this work is to develop and fabricate devices that utilize a hybrid electronic-photonic integration to enable high performance optoelectronic computing and communication systems that overcome the barriers of electronics and dramatically enhance the performance of circuits and systems. We experimentally demonstrate a novel broadband optical time division multiplexer (OTDM) on a silicon chip. The system has a footprint× 700 micrometer and is inherently broadband with a bandwidth of over 100nm making it suitable for high-speed optical networks on chip. Also, we propose and fabricate a novel design to demultiplex the high bit rates of OTDM data using two differentially operated 5Gb/s modulators. Moreover, we propose a high-speed hybrid optical-time-division-multiplexing (OTDM) and wavelength-division-multiplexing (WDM) system that seamlessly generates high bit-rate data (\u3e200Gbit/s) from a low speed (5Gbit/s) quantum-dot mode locked laser pulse source. By utilizing time and wavelength domains, the proposed design is a promising solution for high-speed, compact and low-power consumption optical networks on chip. And finally, we experimentally demonstrate a robust, low insertion loss, compact Silicon ring resonator electro-optic modulator for Binary Phase Shift Key (BPSK) coding/decoding that encodes data in the phase of light. Our design improves significantly over recently demonstrated PSK modulator designs in terms of insertion loss and stability

Digital ADCs and ultra-wideband RF circuits for energy constrained wireless applications by Denis Clarke Daly.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 173-183).Ongoing advances in semiconductor technology have enabled a multitude of portable, low power devices like cellular phones and wireless sensors. Most recently, as transistor device geometries reach the nanometer scale, transistor characteristics have changed so dramatically that many traditional circuits and architectures are no longer optimal and/or feasible. As a solution, much research has focused on developing 'highly digital' circuits and architectures that are tolerant of the increased leakage, variation and degraded voltage headrooms associated with advanced CMOS processes. This thesis presents several highly digital, mixed-signal circuits and architectures designed for energy constrained wireless applications. First, as a case study, a highly digital, voltage scalable flash ADC is presented. The flash ADC, implemented in 0.18 [mu]m CMOS, leverages redundancy and calibration to achieve robust operation at supply voltages from 0.2 V to 0.9 V. Next, the thesis expands in scope to describe a pulsed, noncoherent ultra-wideband transceiver chipset, implemented in 90 nm CMOS and operating in the 3-to-5 GHz band. The all-digital transmitter employs capacitive combining and pulse shaping in the power amplifier to meet the FCC spectral mask without any off-chip filters. The noncoherent receiver system-on-chip achieves both energy efficiency and high performance by employing simple amplifier and ADC structures combined with extensive digital calibration. Finally, the transceiver chipset is integrated in a complete system for wireless insect flight control.(cont.) Through the use of a flexible PCB and 3D die stacking, the total weight of the electronics is kept to 1 g, within the carrying capacity of an adult Manduca sexta moth. Preliminary wireless flight control of a moth in a wind tunnel is demonstrated.Ph.D

Space Shuttle/TDRSS communication and tracking systems analysis

In order to evaluate the technical and operational problem areas and provide a recommendation, the enhancements to the Tracking and Data Delay Satellite System (TDRSS) and Shuttle must be evaluated through simulation and analysis. These enhancement techniques must first be characterized, then modeled mathematically, and finally updated into LinCsim (analytical simulation package). The LinCsim package can then be used as an evaluation tool. Three areas of potential enhancements were identified: shuttle payload accommodations, TDRSS SSA and KSA services, and shuttle tracking system and navigation sensors. Recommendations for each area were discussed

Broadcast-oriented wireless network-on-chip : fundamentals and feasibility

Premi extraordinari doctorat UPC curs 2015-2016, àmbit Enginyeria de les TICRecent years have seen the emergence and ubiquitous adoption of Chip Multiprocessors (CMPs), which rely on the coordinated operation of multiple execution units or cores. Successive CMP generations integrate a larger number of cores seeking higher performance with a reasonable cost envelope. For this trend to continue, however, important scalability issues need to be solved at different levels of design. Scaling the interconnect fabric is a grand challenge by itself, as new Network-on-Chip (NoC) proposals need to overcome the performance hurdles found when dealing with the increasingly variable and heterogeneous communication demands of manycore processors. Fast and flexible NoC solutions are needed to prevent communication become a performance bottleneck, situation that would severely limit the design space at the architectural level and eventually lead to the use of software frameworks that are slow, inefficient, or less programmable. The emergence of novel interconnect technologies has opened the door to a plethora of new NoCs promising greater scalability and architectural flexibility. In particular, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. Most of the resulting Wireless Network-on-Chip (WNoC) proposals have set the focus on leveraging the latency advantage of this paradigm by creating multiple wireless channels to interconnect far-apart cores. This strategy is effective as the complement of wired NoCs at moderate scales, but is likely to be overshadowed at larger scales by technologies such as nanophotonics unless bandwidth is unrealistically improved. This dissertation presents the concept of Broadcast-Oriented Wireless Network-on-Chip (BoWNoC), a new approach that attempts to foster the inherent simplicity, flexibility, and broadcast capabilities of the wireless technology by integrating one on-chip antenna and transceiver per processor core. This paradigm is part of a broader hybrid vision where the BoWNoC serves latency-critical and broadcast traffic, tightly coupled to a wired plane oriented to large flows of data. By virtue of its scalable broadcast support, BoWNoC may become the key enabler of a wealth of unconventional hardware architectures and algorithmic approaches, eventually leading to a significant improvement of the performance, energy efficiency, scalability and programmability of manycore chips. The present work aims not only to lay the fundamentals of the BoWNoC paradigm, but also to demonstrate its viability from the electronic implementation, network design, and multiprocessor architecture perspectives. An exploration at the physical level of design validates the feasibility of the approach at millimeter-wave bands in the short term, and then suggests the use of graphene-based antennas in the terahertz band in the long term. At the link level, this thesis provides an insightful context analysis that is used, afterwards, to drive the design of a lightweight protocol that reliably serves broadcast traffic with substantial latency improvements over state-of-the-art NoCs. At the network level, our hybrid vision is evaluated putting emphasis on the flexibility provided at the network interface level, showing outstanding speedups for a wide set of traffic patterns. At the architecture level, the potential impact of the BoWNoC paradigm on the design of manycore chips is not only qualitatively discussed in general, but also quantitatively assessed in a particular architecture for fast synchronization. Results demonstrate that the impact of BoWNoC can go beyond simply improving the network performance, thereby representing a possible game changer in the manycore era.Avenços en el disseny de multiprocessadors han portat a una àmplia adopció dels Chip Multiprocessors (CMPs), que basen el seu potencial en la operació coordinada de múltiples nuclis de procés. Generacions successives han anat integrant més nuclis en la recerca d'alt rendiment amb un cost raonable. Per a que aquesta tendència continuï, però, cal resoldre importants problemes d'escalabilitat a diferents capes de disseny. Escalar la xarxa d'interconnexió és un gran repte en ell mateix, ja que les noves propostes de Networks-on-Chip (NoC) han de servir un tràfic eminentment variable i heterogeni dels processadors amb molts nuclis. Són necessàries solucions ràpides i flexibles per evitar que les comunicacions dins del xip es converteixin en el pròxim coll d'ampolla de rendiment, situació que limitaria en gran mesura l'espai de disseny a nivell d'arquitectura i portaria a l'ús d'arquitectures i models de programació lents, ineficients o poc programables. L'aparició de noves tecnologies d'interconnexió ha possibilitat la creació de NoCs més flexibles i escalables. En particular, la comunicació intra-xip sense fils ha despertat un interès considerable en virtut de les seva baixa latència, simplicitat, i bon rendiment amb tràfic broadcast. La majoria de les Wireless NoC (WNoC) proposades fins ara s'han centrat en aprofitar l'avantatge en termes de latència d'aquest nou paradigma creant múltiples canals sense fils per interconnectar nuclis allunyats entre sí. Aquesta estratègia és efectiva per complementar a NoCs clàssiques en escales mitjanes, però és probable que altres tecnologies com la nanofotònica puguin jugar millor aquest paper a escales més grans. Aquesta tesi presenta el concepte de Broadcast-Oriented WNoC (BoWNoC), un nou enfoc que intenta rendibilitzar al màxim la inherent simplicitat, flexibilitat, i capacitats broadcast de la tecnologia sense fils integrant una antena i transmissor/receptor per cada nucli del processador. Aquest paradigma forma part d'una visió més àmplia on un BoWNoC serviria tràfic broadcast i urgent, mentre que una xarxa convencional serviria fluxos de dades més pesats. En virtut de la escalabilitat i del seu suport broadcast, BoWNoC podria convertir-se en un element clau en una gran varietat d'arquitectures i algoritmes poc convencionals que milloressin considerablement el rendiment, l'eficiència, l'escalabilitat i la programabilitat de processadors amb molts nuclis. El present treball té com a objectius no només estudiar els aspectes fonamentals del paradigma BoWNoC, sinó també demostrar la seva viabilitat des dels punts de vista de la implementació, i del disseny de xarxa i arquitectura. Una exploració a la capa física valida la viabilitat de l'enfoc usant tecnologies longituds d'ona milimètriques en un futur proper, i suggereix l'ús d'antenes de grafè a la banda dels terahertz ja a més llarg termini. A capa d'enllaç, la tesi aporta una anàlisi del context de l'aplicació que és, més tard, utilitzada per al disseny d'un protocol d'accés al medi que permet servir tràfic broadcast a baixa latència i de forma fiable. A capa de xarxa, la nostra visió híbrida és avaluada posant èmfasi en la flexibilitat que aporta el fet de prendre les decisions a nivell de la interfície de xarxa, mostrant grans millores de rendiment per una àmplia selecció de patrons de tràfic. A nivell d'arquitectura, l'impacte que el concepte de BoWNoC pot tenir sobre el disseny de processadors amb molts nuclis no només és debatut de forma qualitativa i genèrica, sinó també avaluat quantitativament per una arquitectura concreta enfocada a la sincronització. Els resultats demostren que l'impacte de BoWNoC pot anar més enllà d'una millora en termes de rendiment de xarxa; representant, possiblement, un canvi radical a l'era dels molts nuclisAward-winningPostprint (published version