854 research outputs found

    Multi-port Memory Design for Advanced Computer Architectures

    Get PDF
    In this thesis, we describe and evaluate novel memory designs for multi-port on-chip and off-chip use in advanced computer architectures. We focus on combining multi-porting and evaluating the performance over a range of design parameters. Multi-porting is essential for caches and shared-data systems, especially multi-core System-on-chips (SOC). It can significantly increase the memory access throughput. We evaluate FinFET voltage-mode multi-port SRAM cells using different metrics including leakage current, static noise margin and read/write performance. Simulation results show that single-ended multi-port FinFET SRAMs with isolated read ports offer improved read stability and flexibility over classical double-ended structures at the expense of write performance. By increasing the size of the access transistors, we show that the single-ended multi-port structures can achieve equivalent write performance to the classical double-ended multi-port structure for 9% area overhead. Moreover, compared with CMOS SRAM, FinFET SRAM has better stability and standby power. We also describe new methods for the design of FinFET current-mode multi-port SRAM cells. Current-mode SRAMs avoid the full-swing of the bitline, reducing dynamic power and access time. However, that comes at the cost of voltage drop, which compromises stability. The design proposed in this thesis utilizes the feature of Independent Gate (IG) mode FinFET, which can leverage threshold voltage by controlling the back gate voltage, to merge two transistors into one through high-Vt and low-Vt transistors. This design not only reduces the voltage drop, but it also reduces the area in multi-port current-mode SRAM design. For off-chip memory, we propose a novel two-port 1-read, 1-write (1R1W) phasechange memory (PCM) cell, which significantly reduces the probability of blocking at the bank levels. Different from the traditional PCM cell, the access transistors are at the top and connected to the bitline. We use Verilog-A to model the behavior of Ge2Sb2Te5 (GST: the storage component). We evaluate the performance of the two-port cell by transistor sizing and voltage pumping. Simulation results show that pMOS transistor is more practical than nMOS transistor as the access device when both area and power are considered. The estimated area overhead is 1.7ďż˝, compared to single-port PCM cell. In brief, the contribution we make in this thesis is that we propose and evaluate three different kinds of multi-port memories that are favorable for advanced computer architectures

    Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

    Get PDF
    CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

    Multiple facets of tightly coupled transducer-transistor structures

    Get PDF
    The ever increasing demand for data processing requires different paradigms for electronics. Excellent performance capabilities such as low power and high speed in electronics can be attained through several factors including using functional materials, which sometimes acquire superior electronic properties. The transduction-based transistor switching mechanism is one such possibility, which exploits the change in electrical properties of the transducer as a function of a mechanically induced deformation. Originally developed for deformation sensors, the technique is now moving to the centre stage of the electronic industry as the basis for new transistor concepts to circumvent the gate voltage bottleneck in transistor miniaturization. In issue 37 of Nanotechnology, Chang et al show the piezoelectronic transistor (PET), which uses a fast, low-power mechanical transduction mechanism to propagate an input gate voltage signal into an output resistance modulation. The findings by Chang et al will spur further research into piezoelectric scaling, and the PET fabrication techniques needed to advance this type of device in the future

    Comparing the impact of power supply voltage on CMOS-and FinFET-based SRAMs in the presence of resistive defects

    Get PDF
    CMOS technology scaling has reached its limit at the 22 nm technology node due to several factors including Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE). In order to continue the miniaturization process via technology down-scaling while preserving system reliability and performance, Fin Field-Effect Transistors (FinFETs) arise as an alternative to CMOS transistors. In parallel, Static Random-Access Memories (SRAMs) increasingly occupy great part of Systems-on-Chips’ (SoCs) silicon area, making their reliability an important issue. SRAMs are designed to reach densities at the limit of the manufacturing process, making this component susceptible to manufacturing defects, including the resistive ones. Such defects may cause dynamic faults during the circuits’ lifetime, an important cause of test escape. Thus, the identification of the proper faulty behavior taking different operating conditions into account is considered crucial to guarantee the development of more suitable test methodologies. In this context, a comparison between the behavior of a 22 nm CMOS-based and a 20 nm FinFET-based SRAM in the presence of resistive defects is carried out considering different power supply voltages. In more detail, the behavior of defective cells operating under different power supply voltages has been investigated performing SPICE simulations. Results show that the power supply voltage plays an important role in the faulty behavior of both CMOS- and FinFET-based SRAM cells in the presence of resistive defects but demonstrate to be more expressive when considering the FinFET-based memories. Studying different operating temperatures, the results show an expressively higher occurrence of dynamic faults in FinFET-based SRAMs when compared to CMOS technology

    Review on suitable eDRAM configurations for next nano-metric electronics era

    Get PDF
    We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform their memory cell counterparts, we explored different technological proposals and operational regimes where it can be located. The best memory cell performance is observed for the 3T1D-eDRAM cell when it is based on FinFET devices. Both device variability and SEU appear as key reliability issues for memory cells at sub-22nm technology node.Peer ReviewedPostprint (author's final draft

    Study of Warm Electron Injection in Double Gate SONOS by Full Band Monte Carlo Simulation

    Full text link
    In this paper we investigate warm electron injection in a double gate SONOS memory by means of 2D full-band Monte Carlo simulations of the Boltzmann Transport Equation (BTE). Electrons are accelerated in the channel by a drain-to-source voltage VDS smaller than 3 V, so that programming occurs via electrons tunneling through a potential barrier whose height has been effectively reduced by the accumulated kinetic energy. Particle energy distribution at the semiconductor/oxide interface is studied for different bias conditions and different positions along the channel. The gate current is calculated with a continuum-based post-processing method as a function of the particle distribution obtained from Monte Carlo. Simulation results show that the gate current increases by several orders of magnitude with increasing drain bias and warm electron injection can be an interesting option for programming when short channel effects prohibit the application of larger drain bias

    Performance Analysis of FinFET Based Inverter circuit, NAND and NOR Gate at 22nm and 14nm Node technologies.

    Get PDF
    The size of integrated devices such as PC, mobiles etc are reducing day by day with multiple operations, all of these is happening because of the scaling down the size of MOSFETs which is the main component in memory, processors and so on. As we scale down the MOSFETs to the nanometer regime the short channel effects arises which degrades the system performance and reliability. Here in this paper we describe the alternative MOSFET called FinFET which reduces the short channel effects and its performance analysis of digital applications such as inverter circuit, nand and nor gates at 22nm and 14nm node technologies. DOI: 10.17762/ijritcc2321-8169.15050
    • …
    corecore