Multiport VNA Measurements

This article presents some of the most recent multiport VNA measurement methodologies used to characterize these highspeed digital networks for signal integrity. There will be a discussion of the trends and measurement challenges of high-speed digital systems, followed by a presentation of the multiport VNA measurement system details, calibration, and measurement techniques, as well as some examples of interconnect device measurements. The intent here is to present some general concepts and trends for multiport VNA measurements as applied to computer system board-level interconnect structures, and not to promote any particular brand or produc

Signal Integrity Analysis for High Speed Digital Circuit

This dissertation report marks the commencement of the Final Year Project (FYP) titled Signal Integrity Analysis for High Speed Digital Circuit. This project is a study on various signal integrity (SI) issues that could possibly come into play on Printed Circuit Boards (PCBs). This project is conducted to analyze and grasp a better understanding on the nature of the problem, how the problem is manifested in circuits and what design solutions can be employed to minimize its effects. Such a study is not something new but is definitely getting more crucial as the vast improvement in chip fabrication technology leads to logic families operating at a much higher speed, resulting to a faster rise time which will worsen the noise phenomena, i. e. reflection, crosstalk, and power system stability during component switching. Several causes to signal integrity issues on the printed circuit boards are analyzed and both proper and improper circuit design techniques are implemented on the Advanced Design System (ADS) software for data collection and analysis. Deliverables at the end this project would be the simulation results to support the study, whereby several simulations are conducted to demonstrate and verify the theoretical study of signal integrity issues. Besides that, the designs will then be fabricated on a two-layer microstrip board and tested on the Digital Communication Analyzer (DCA) to obtain more practical results. A project Gantt chart is attached in the appendix to illustrate the work flow and anticipated progress

Novel Multicarrier Memory Channel Architecture Using Microwave Interconnects: Alleviating the Memory Wall

abstract: The increase in computing power has simultaneously increased the demand for input/output (I/O) bandwidth. Unfortunately, the speed of I/O and memory interconnects have not kept pace. Thus, processor-based systems are I/O and interconnect limited. The memory aggregated bandwidth is not scaling fast enough to keep up with increasing bandwidth demands. The term "memory wall" has been coined to describe this phenomenon. A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. The memory bus is formed using a microwave signal carried within a waveguide. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format or higher. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We pioneered the usage of SIW as memory channel interconnects and demonstrated that it alleviates the memory bandwidth bottleneck. We demonstrated SIW performance superiority over conventional transmission line in immunity to cross-talk and electromagnetic interference. We developed a methodology based on design of experiment (DOE) and response surface method techniques that optimizes the design of SIW interconnects and minimizes its performance fluctuations under material and manufacturing variations. Along with using SIW, we implemented a multicarrier architecture which enabled the aggregated DDR bandwidth to reach 30 Gbit/s. We developed an end-to-end system model in Simulink and demonstrated the MCMCA performance for ultra-high throughput memory channel. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW interconnect is sufficient to transmit the 64 DDR bits. Overall aggregated bus data rate achieves 240 GBytes/s data transfer with EVM not exceeding 2.26% and phase error of 1.07 degree or less.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Design Optimization of Full-Wave EM Models by Low-Order Low-Dimension Polynomial Surrogate Functionals

A practical formulation for EM-based design optimization of high-frequency circuits using simple polynomial surrogate functionals is proposed in this paper. Our approach starts from a careful selection of design variables and is based on a closed-form formulation that yields global optimal values for the surrogate model weighting factors, avoiding a large set of expensive EM model data, and resulting in accurate low-order low-dimension polynomials interpolants that are used as vehicles for efficient design optimization. Our formulation is especially suitable for EM-based design problems with no equivalent circuital models available. The proposed technique is illustrated by the EM-based design optimization of a Ka-band substrate integrated waveguide (SIW) interconnect with conductor-backed coplanar waveguide (CBCPW) transitions, a low crosstalk PCB microstrip interconnect structure with guard traces, and a 10-40 GHz SIW interconnect with microstrip transitions on a standard FR4-based substrate. Three commercially available full-wave EM solvers are used in our examples: CST, Sonnet and COMSOL

Common-mode noise reduction schemes for weakly coupled differential serpentine delay microstrip lines

This paper proposes design schemes to reduce the common mode noise from weakly coupled differential serpentine delay microstrip lines (DSDMLs). The proposed approach is twofold: we leverage strongly coupled vertical-turn-coupled traces (VTCTs) instead of weakly coupled VTCTs (conventional pattern) and add guard traces. Time- and frequency-domain analyses of the proposed schemes for reducing the common-mode noise are performed by studying the transmission waveform and the differential-to-common mode conversion using the circuit solver HSPICE and the 3-D full-wave simulator HFSS, respectively. Compared to the conventional design of the weakly coupled DSDMLs, the proposed solutions yield a reduction of about 54% of the peak-to-peak amplitude of the common-mode noise, while the differential impedance remains matched along the complete length of the DSDML. Moreover, the range of frequencies, over which the magnitude of the differential-to-common mode conversion is now significantly reduced, is very wide, i.e. about 0.3-10 GHz. Furthermore, the differential insertion and reflection loss introduced by the newly proposed designs are almost the same as the ones achieved by using the conventional design. Finally, a favorable comparison between simulated and measured results confirms the excellent common-mode noise reduction performance of the proposed schemes

Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity

As we enter the 5G (5th-Generation) era, the amount of information and data has become increasingly tremendous. Therefore, electronic circuits need to have higher chip density, faster operating speed and better signal quality of transmission. As the carrier of electronic components, the design difficulty of high-speed PCB (Printed Circuit Board) is also increasing. Equal-length wiring is an essential part of PCB design. But now, it can no longer meet the needs of designers. Accordingly, in view of the shortcomings of the traditional equal-length wiring, this article proposes two optimization ways: the "spiral wiring" way and the "double spiral wiring" way. Based on the theoretical analysis of the transmission lines, the two optimization ways take the three aspects of optimizing the layout and wiring space, suppressing crosstalk and reducing reflection as the main points to optimize the design. Eventually, this article performs simulation and verification of schematic diagram and PCB of the optimal design by using HyperLynx simulation software. The simulation results show that these two ways not only improve the flexibility of the transmission line layout, but also improve the signal integrity of the transmission lines. Of course, this also proves the feasibility and reliability of the two optimized designs

Development of a non-iterative macromodeling technique by data integration and least square method

In this paper, a new method is introduced to synthesize the original data obtained from simulation or measurement results in the form of a rational function. The integration of the available data is vital to the performance of the proposed method. The values of poles and residues of the rational model are determined by solving the system of linear equations using conventional Least Square Method (LSM). To ensure the stability condition of the provided model, a controller coefficient is considered. Also, using this parameter, the designer can increase the stability margin of a system with poor stability conditions. The introduced method has the potential to be used for a wide range of practical applications since there is no specific restriction on the use of this method. The only requirement that should be considered is Dirichlet condition for the original data, usually the case for physical systems. To verify the performances of the proposed method, several application test cases were investigated and the obtained results were compared with those gathered by the well-known vector fitting algorithm. Also, the examinations showed that the method is efficient in the presence of noisy data

Anticipating EMI from Coupling Between High-Speed Digital and I/O Lines

The increasing speed of digital circuit design as well as the density of printed circuit board (PCB) layouts often result in more challenging electromagnetic interference (EMI) problems. The coupling between a high-speed digital line and an I/O line can be a primary EMI coupling path, and the attached cable a dominant radiator. This mechanism is studied and modeled herein in a multi-stage modeling fashion. EMI modeling is developed for coupling between the transmission lines, and the attached cable as the EMI antenna. Finally, the EMI is calculated for the coupled noise driving the attached cable. The agreement between the modeled and measured results demonstrates that the modeling method is suitable for estimating the EMI due to high-frequency coupling to I/O lines