Delta-Sigma Modulator based Compact Sensor Signal Acquisition Front-end System

The proposed delta-sigma modulator ($\Delta\Sigma$M) based signal acquisition architecture uses a differential difference amplifier (DDA) customized for dual purpose roles, namely as instrumentation amplifier and as integrator of $\Delta\Sigma$M. The DDA also provides balanced high input impedance for signal from sensors. Further, programmable input amplification is obtained by adjustment of $\Delta\Sigma$M feedback voltage. Implementation of other functionalities, such as filtering and digitization have also been incorporated. At circuit level, a difference of transconductance of DDA input pairs has been proposed to reduce the effect of input resistor thermal noise of front-end R-C integrator of the $\Delta\Sigma$M. Besides, chopping has been used for minimizing effect of Flicker noise. The resulting architecture is an aggregation of functions of entire signal acquisition system within the single block of $\Delta\Sigma$M, and is useful for a multitude of dc-to-medium frequency sensing and similar applications that require high precision at reduced size and power. An implementation of this in 0.18-$\mu$m CMOS process has been presented, yielding a simulated peak signal-to-noise ratio of 80 dB and dynamic range of 109dBFS in an input signal band of 1 kHz while consuming 100 $\mu$W of power; with the measured signal-to-noise ratio being lower by about 9 dB.Comment: 13 pages, 16 figure

On chopper effects in discrete-time ΣΔ modulators

Analog-to-digital converters based on ΣΔ modulators are used in a wide variety of applications. Due to their inherent monotonous behavior, high linearity, and large dynamic range, they are often the preferred option for sensor and instrumentation. Offset and flicker noise are usual concerns for this type of applications, and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Due to its simple operation principle, the action of the chopper in the integrator is often overlooked. In this paper, we provide an analytical study of the static effects in ΣΔ modulators, which shows that the introduction of chopper is not transparent to the modulator operation and should thus be designed with care.Gobierno de España TEC-2007-68072Consejo Superior de Investigaciones Científicas 200850I21

On chopper effects in discrete-time ΣΔ modulators

Analog-to-digital converters based on ΣΔ modulators are used in a wide variety of applications. Due to their inherent monotonous behavior, high linearity, and large dynamic range, they are often the preferred option for sensor and instrumentation. Offset and flicker noise are usual concerns for this type of applications, and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Due to its simple operation principle, the action of the chopper in the integrator is often overlooked. In this paper, we provide an analytical study of the static effects in ΣΔ modulators, which shows that the introduction of chopper is not transparent to the modulator operation and should thus be designed with care.This work has been partially funded by the Spanish Government project TEC-2007-68072 and the CSIC project 200850I213.Peer reviewe

A Robust 96.6-dB-SNDR 50-kHz-Bandwidth Switched-Capacitor Delta-Sigma Modulator for IR Imagers in Space Instrumentation

Infrared imaging technology, used both to study deep-space bodies' radiation and environmental changes on Earth, experienced constant improvements in the last few years, pushing data converter designers to face new challenges in terms of speed, power consumption and robustness against extremely harsh operating conditions. This paper presents a 96.6-dB-SNDR (Signal-to-Noise-plus-Distortion Ratio) 50-kHz-bandwidth fourth-order single-bit switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW fit for space instrumentation. The circuit features novel Class-AB single-stage switched variable-mirror amplifiers (SVMAs) enabling low-power operation, as well as low sensitivity to both process and temperature deviations for the whole modulator. The physical implementation resulted in a 1.8-mm 2 chip integrated in a standard 0.18-μm 1-poly-6-metal (1P6M) CMOS technology, and it reaches a 164.6-dB Schreier figure of merit from experimental SNDR measurements without making use of any clock bootstrapping, analog calibration, nor digital compensation technique. When coupled to a IR imager, the current design allows more than 50 frames per minute with a resolution of 16 effective number of bits (ENOB) while consuming less than 300 mW

A high precision fully integrated accelerometer

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.Includes bibliographical references (p. 193-196).by Michael Anthony Ashburn, Jr.M.S

Integrated system for a high resolution MEMS accelerometer

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 201

Time-encoding analog-to-digital converters : bridging the analog gap to advanced digital CMOS : part 1: basic principles

The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs. The shrinking supply voltage and presence of mismatch and noise restrain the dynamic range, causing analog circuits to be large in area and have a high power consumption in spite of the process scaling. Analog circuits based on time encoding [1], [2] and hybrid analog/digital signal processing [3] have been developed to overcome these issues. Realizing analog circuit functionality with highly digital circuits results in more scalable design solutions that can achieve excellent performance. This article reviews the basic principles of time encoding applied, in particular, to analog-to-digital converters (ADCs) based on voltage-controlled oscillators (VCOs), one of the most successful time-encoding techniques to date

An Oversampled Analog To Digital Converter For Acquiring Neural Signals

A third order delta-sigma modulator and associated low-pass digital filter is designed for an analog to digital converter: ADC) for sensing bioelectric phenomena. The third order noise shaping reduces the quantization noise in the baseband and the digital lowpass filter greatly attenuates the out of band quantization noise, increasing the effective number of bits. As part of a neural signal acquisition system designed by The BrainScope Company to capture Electro-Encephalogram: EEG) and Automated Brainstem Response: ABR) signals, this paper describes the design of a third order Delta-Sigma modulator which meets or exceeds the low noise specifications mandated by previous BrainScope products. The third order cascaded delta-sigma modulator attains a resolution of 12.3 bits in a signal bandwidth of 3kHz and 14.9 bits in a signal bandwidth of 100Hz, operating from a +/- 1.76V reference with a 250kHz clock

A Low-Power Sigma-Delta Modulator for Healthcare and Medical Diagnostic Applications

This paper presents a switched-capacitor Sigma-Delta modulator designed in 90-nm CMOS technology, operating at 1.2-V supply voltage. The modulator targets healthcare and medical diagnostic applications where the readout of small-bandwidth signals is required. The design of the proposed A/D converter was optimized to achieve the minimum power consumption and area. A remarkable performance improvement is obtained through the integration of a low-noise amplifier with modified Miller compensation and rail-to-rail output stage. The manuscript also presents a set of design equations, from the small-signal analysis of the amplifier, for an easy design of the modulator in different technology nodes. The Sigma-Delta converter achieves a measured 96-dB dynamic range, over a 250-Hz signal bandwidth, with an oversampling ratio of 500. The power consumption is 30 μW, with a silicon area of 0.39 mm²