Correlation of drain breakdown with excess noise and other surface-related phenomena in enhancement MOSFETS

An investigation of semiconductor surface-related phenomena has been undertaken to correlate 1/F noise with drain breakdown in P-channel enhancement MOSFET\u27s. Increases in the intensity of drain current fluctuations at 10Hz and at 1KHz, particularly at the higher frequency, was observed following accelerated life-testing for threshold voltage drift. It was also concluded that mobile ions near the oxide-semiconductor interface produce a sharp increase in fast trapping centers. It was also found that 1/F noise intensity consistently peaked at the threshold of drain breakdown and that it steadily decreased with further increases in drain current. Of all the transistors tested, those with relatively low noise intensity were found to exhibit sharper breakdown characteristics and higher breakdown voltages while those transistors with high noise showed soft breakdown characteristics. It was therefore concluded that the low noise MOS transistors are superior to those with relatively high noise and that the 1/F noise-drain current characteristics may be used in nondestructive testing to determine the approximate drain breakdown voltage

Correlation of 1/f noise with threshold drift in MOSFET\u27s

A brief review of the fundamentals of MOSFET\u27s is given. A correlation between threshold drift and surface states is made, with a following correlation between surface states and 1/f noise. It therefore follows that MOSFET\u27s with a high 1/f noise level will drift more than those with a low level of 1/f noise. Experiments were carried out to show this effect, but no clear cut conclusions can be drawn from the experimental work

Reliability of MOS devices : threshold voltage instability

A very important factor in the reliability of MOS devices is the stability of the threshold voltage. This dissertation examines the effects of positive and negative gate bias stresses at elevated temperatures on the drift in the threshold voltage of MOS field effect transistors. Over 400 p-channel enhancement mode devices were life tested under different temperature and gate bias conditions for periods of up to 15,000 hours, and the drift in their threshold voltages studied and analyzed. It was found that under both negative and positive bias-temperature tests, the threshold voltage drifted towards more negative values, though in the negative bias tests, the drift in the first few tens or hundreds of hours was in the opposite direction. The effect of positive bias is easily explained in terms of impurity ion migration effects. To explain the effect of negative bias, two competing mechanisms, namely, impurity ion migration and the silicon ion effects, are postulated by the author; and a logical theoretical explanation is developed to explain the results of the experimental investigation

Hot electron currents in MOSFETs.

Silicon has become the material of choice for fabrication of high circuit density, low defect density and high speed integration devices. CMOS technology has been favoured as an attractive candidate to take advantage of the performance enhancements available through miniturisation. However, hot carrier effects in general, and hot electron currents in particular, are posing as the main obstacle to a new era of sub-micron architecture in semiconductor device technology. Electron transport in modern sub-micron device is often governed by mechanisms that were not relevant to long-channel devices. Many of the classical device models are based upon such convenient assumptions as "thermal equilibrium" and "uniform local electric field". With the downscaling of devices, hot electron currents are becoming increasingly inherent. These currents arise from the fact that electrical fields in small geometry devices can reach very high values and can vary rapidly in space. The large electric field can Impart significant kinetic energies to the carriers. In thermal equilibrium, all elementary excitations in a semiconductor (eg. Electrons, holes, phonons) can be characterised by a temperature that is the same as the lattice temperature. Under the influence of large electric fields, however, the distribution function of these elementally excitations deviate from those in thermal equilibrium. The term "Hot Carriers" is often used to describe these non-equilibrium situations. In this thesis hot electron currents, in particular their physical origins and dependence upon various operational and geometrical parameters, have been discussed and then quantified in a number of models based on the "Lucky Drift" theory of transport. Temperature is then used as a tool to differentiate between the underlying physical processes, and to determine if reliability problems related to hot electron effects would improve under cryogenic operation. It has been the prime objective of this work from the outset to concentrate on the study of N-channel devices. This is primarily due to the fact that N-channel MOSFET's are more prone to hot electron effects, and therefore, studies in the nature of this enhanced susceptibility could prove to be more fruitful

Influence of material quality and process-induced defects on semiconductor device performance and yield

An overview of major causes of device yield degradation is presented. The relationships of device types to critical processes and typical defects are discussed, and the influence of the defect on device yield and performance is demonstrated. Various defect characterization techniques are described and applied. A correlation of device failure, defect type, and cause of defect is presented in tabular form with accompanying illustrations

Design of a reliability methodology: Modelling the influence of temperature on gate Oxide reliability

An Integrated Reliability Methodology (IRM) is presented that encompasses the changes that technology growth has brought with it and includes several new device degradation models. Each model is based on a physics of failure approach and includes on the effects of temperature. At all stages the models are verified experimentally on modern deep sub-micron devices. The research provides the foundations of a tool which gives the user the opportunity to make appropriate trade-offs between performance and reliability, and that can be implemented in the early stages of product development

The study of SiGe-channel heterojunction MOS device

The advances in the growth of pseudomorphic silicon-germanium epitaxial layer combined with the strong need for high-speed CMOS VLSI circuit have led to increased interest in silicon-based heterojunction MOSFET\u27s transistors. The high-performance heterostructure SiGe MOSFET exhibits higher channel mobility than its bulk Si counterpart. The most critical and challenging process for fabricating a SiGe MOSFET device is that for making a gate oxide with sufficient quality for useful conductivity modulation. PECVD methods was employed to deposit the gate oxide and C-V method was used to investigate the electrical characteristics of the film. For PECVD gate oxide, a film refractive index 1.47 were obtained using the deposition rate 125Å/min with a break down voltage 4-5 MV/cm, which deposition conditions are optimized as flow rate of DES (12sccm), N20(172sccm), Helium(850sccm), temperature 300°C, power density 0.09W/cm2. The total interface trap and fixed charge density Nt=5.4x1012 cm-2 and flatband voltage Vfb=-16V for non-armealing MOS capacitor and the total effect of interface trap and fixed charge density 6.4x1011 cm-2 and flatband voltage 4V were obtained at the oxide thickness dox=1160Å using annealing at 650°C for 30 minutes in the ambient of nitrogen. LPCVD silicon dioxide film was obtained at the deposition rate 14.5 Å/min and refractive index 1.46 while Nt=3.9x1012cm-2 and Vfb=-8V for nonannealing and Nt=4.9x1011 cm-2 and Vfb=-2V for 650°C annealed MOS capacitor