Controller Area Network

Controller Area Network (CAN) is a popular and very well-known bus system, both in academia and in industry. CAN protocol was introduced in the mid eighties by Robert Bosch GmbH [7] and it was internationally standardized in 1993 as ISO 11898-1 [24]. It was initially designed to distributed automotive control systems, as a single digital bus to replace traditional point-to-point cables that were growing in complexity, weight and cost with the introduction of new electrical and electronic systems. Nowadays CAN is still used extensively in automotive applications, with an excess of 400 million CAN enabled microcontrollers manufactured each year [14]. The widespread and successful use of CAN in the automotive industry, the low cost asso- ciated with high volume production of controllers and CAN's inherent technical merit, have driven to CAN adoption in other application domains such as: industrial communications, medical equipment, machine tool, robotics and in distributed embedded systems in general. CAN provides two layers of the stack of the Open Systems Interconnection (OSI) reference model: the physical layer and the data link layer. Optionally, it could also provide an additional application layer, not included on the CAN standard. Notice that CAN physical layer was not dened in Bosch original specication, only the data link layer was dened. However, the CAN ISO specication lled this gap and the physical layer was then fully specied. CAN is a message-oriented transmission protocol, i.e., it denes message contents rather than nodes and node addresses. Every message has an associated message identier, which is unique within the whole network, dening both the content and the priority of the message. Transmission rates are dened up to 1 Mbps. The large installed base of CAN nodes with low failure rates over almost two decades, led to the use of CAN in some critical applications such as Anti-locking Brake Systems (ABS) and Electronic Stability Program (ESP) in cars. In parallel with the wide dissemination of CAN in industry, the academia also devoted a large eort to CAN analysis and research, making CAN one of the must studied eldbuses. That is why a large number of books or book chapters describing CAN were published. The rst CAN book, written in French by D. Paret, was published in 1997 and presents the CAN basics [32]. More implementation oriented approaches, including CAN node implementation and application examples, can be found in Lorenz [28] and in Etschberger [16], while more compact descriptions of CAN can be found in [11] and in some chapters of [31]. Despite its success story, CAN application designers would be happier if CAN could be made faster, cover longer distances, be more deterministic and more dependable [34]. Over the years, several protocols based in CAN were presented, taking advantage of some CAN properties and trying to improve some known CAN drawbacks. This chapter, besides presenting an overview of CAN, describes also some other relevant higher level protocols based on CAN, such as CANopen [13], DeviceNet [6], FTT-CAN [1] and TTCAN [25]

Spacelab system analysis: A study of the Marshall Avionics System Testbed (MAST)

An analysis of the Marshall Avionics Systems Testbed (MAST) communications requirements is presented. The average offered load for typical nodes is estimated. Suitable local area networks are determined

Improved 3-Line Hardware Synchronization

A new procedure is proposed to synchronize processors of a distributed system, which concurrently execute a common process consisting of a sequence of operations. The procedure is an extension of that used for the 1987 IEEE Futurebus Standard. It is based on global synchronization lines and a distributed synchronizer, and requires only minor modifications of existing hardware. The procedure allows to carry out two alternative synchronization protocols. As usual, an operation may be terminated by the last processor having finished its part of the operation. Alternatively, the operation may also be terminated by the first processor being ready. Application of this second procedure, e.g., to bus arbitration, allows to reduce the arbitration time in average by a factor of 2

Spacelab system analysis: A study of communications systems for advanced launch systems

An analysis of the required performance of internal avionics data bases for future launch vehicles is presented. Suitable local area networks that can service these requirements are determined

Integrated voice/data through a digital PBX

The digital voice/data PBX is finally reaching its anticipated potential and becoming a major factor when considering the total communications picture for many businesses today. The digital PBX has always been the choice for voice communications but has lagged behind the LAN industry when it comes to data transfers. The pendulum has begun to swing with the enhanced data capabilities of third and fourth generation PBXs. The battle for the total communication market is quite fierce between the LAN and PBX vendors now. This research thesis looks at the history, evolution, and architecture of voice/data PBXs. It traces development of PBXs through the present fourth generation architectures. From the first manual switches introduced in the late 1800\u27s through the Strowger switch, step-by-step switching, stored program control, common control, digital switches, dual bus architectures, and finally what is anticipated in the future. A detailed description of the new fourth generation dual bus architectures is presented. Lastly, speculations on the future direction PBX architectures will take is explored. A description of the mechanics of a possible Wave Division PBX is presented based on a fiber optic transport system

Design and Analysis of Router Architectures for NoC

The advance of process technology keeps on reducing the device size. As a result, the number of processing elements that can be integrated on a single chip (SoC) increases. The reduction in the device size also reducing the gate delay compared to the wire delay giving rise to increase in the frequency of operation of the devices. Further, in order to reduce the design time to market the communication system must support the plug and play architecture and should support design reuse. The conventional on-chip communication architecture, which consists of point-to-point connection and bus infrastructure, may not be able to provide sufficient communication requirements for SoC in terms of increasing the frequency of operation, providing reliability and flexibility. Further, conventional communication systems used for on-chip communication are not scalable and does not support design reuse. The NOC design represents a new paradigm to design multi-processor SoC which is scalable and supports design reuse. The NOC architecture uses layered protocols and packet switched networks which consist of on-chip routers, links and network interface on a predefined topology. NoC requires many on-chip resources which can increase the cost, area and power consumption. The efficiency of the NoC depends on how the resources are utilized for traversing the packet from source to destination which is determined by the flow control mechanism. The components which are used in the NoC for establishing communication between the modules of SoC were designed using VERILOG HDL. Different types of router architectures used by NoC were also designed mentioning their merits and demerits and their area and power consumption was also estimate

Network Interface Design for Network-on-Chip

In the culture of globalized integrated circuit (IC, a.k.a chip) production, the use of Intellectual Property (IP) cores, computer aided design tools (CAD) and testing services from un-trusted vendors are prevalent to reduce the time to market. Unfortunately, the globalized business model potentially creates opportunities for hardware tampering and modification from adversary, and this tampering is known as hardware Trojan (HT). Network-on-chip (NoC) has emerged as an efficient on-chip communication infrastructure. In this work, the security aspects of NoC network interface (NI), one of the most critical components in NoC will be investigated and presented. Particularly, the NI design, hardware attack models and countermeasures for NI in a NoC system are explored. An OCP compatible NI is implemented in an IBM0.18ìm CMOS technology. The synthesis results are presented and compared with existing literature. Second, comprehensive hardware attack models targeted for NI are presented from system level to circuit level. The impact of hardware Trojans on NoC functionality and performance are evaluated. Finally, a countermeasure method is proposed to address the hardware attacks in NIs