Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS

In questo lavoro si presenta una metodologia di progettazione elettronica a livello di sistema, affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di equazioni atti a selezionare le configurazione di interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre, il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso

Systematic Comparison of HF CMOS Transconductors

Transconductors are commonly used as active elements in high-frequency (HF) filters, amplifiers, mixers, and oscillators. This paper reviews transconductor design by focusing on the V-I kernel that determines the key transconductor properties. Based on bandwidth considerations, simple V-I kernels with few or no internal nodes are preferred. In a systematic way, virtually all simple kernels published in literature are generated. This is done in two steps: 1) basic 3-terminal transconductors are covered and 2) then five different techniques to combine two of them in a composite V-I kernel. In order to compare transconductors in a fair way, a normalized signal-to-noise ratio (NSNR) is defined. The basic V-I kernels and the five classes of composite V-I kernels are then compared, leading to insight in the key mechanisms that affect NSNR. Symbolic equations are derived to estimate NSNR, while simulations with more advanced MOSFET models verify the results. The results show a strong tradeoff between NSNR and transconductance tuning range. Resistively generated MOSFETs render the best NSNR results and are robust for future technology developments

Highly efficient linear CMOS power amplifiers for wireless communications

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.PhDCommittee Chair: Kenney, J. Stevenson; Committee Member: Jongman Kim; Committee Member: Kohl, Paul A.; Committee Member: Kornegay, Kevin T.; Committee Member: Lee, Chang-H

Realization of Resistorless Lossless Positive and Negative Grounded Inductor Simulators Using Single ZC-CCCITA

This paper is in continuation with the very recent work of Prasad et al. [14], wherein new realizations of grounded and floating positive inductor simulator using current differencing transconductance amplifier (CDTA) are reported. The focus of the paper is to provide alternate realizations of lossless, both positive and negative inductor simulators (PIS and NIS) in grounded form using z-copy current-controlled current inverting transconductance amplifier (ZC-CCCITA), which can be considered as a derivative of CDTA, wherein the current differencing unit (CDU) is reduced to a current-controlled current inverting unit. We demonstrate that only a single ZC-CCCITA and one grounded capacitor are sufficient to realize grounded lossless PIS or NIS. The proposed circuits are resistorless whose parameters can be controlled through the bias currents. The workability of the proposed PIS is validated by SPICE simulations on three RLC prototypes

Modelling, Analysis and Design of Optimised Electronic Circuits for Visible Light Communication Systems

This thesis explores new circuit design techniques and topologies to extend the bandwidth of visible light communication (VLC) transmitters and receivers, by ameliorating the bandwidth-limiting effects of commonly used optoelectronic devices. The thesis contains detailed literature review of transmitter and receiver designs, which inspired two directions of work. The first proposes new designs of optically lossless light emitting diode (LED) bandwidth extension technique that utilises a negative capacitance circuit to offset the diode’s bandwidth-limiting capacitance. The negative capacitance circuit was studied and verified through newly developed mathematical analysis, modelling and experimental demonstration. The bandwidth advantage of the proposed technique was demonstrated through measurements in conjunction with several colour LEDs, demonstrating up to 500% bandwidth extension with no loss of optical power. The second direction of work enhances the bandwidth of VLC receivers through new designs of ultra-low input impedance transimpedance amplifiers (TIAs), designed to be insensitive to the high photodiode capacitances (Cpd) of large area detectors. Moreover, the thesis proposes a new circuit, which modifies the traditional regulated cascode (RGC) circuit to enhance its bandwidth and gain. The modified RGC amplifier efficiently treats significant RGC inherent bandwidth limitations and is shown, through mathematical analysis, modelling and experimental measurements to extend the bandwidth further by up to 200%. The bandwidth advantage of such receivers was demonstrated in measurements, using several large area photodiodes of area up to 600 mm^2, resulting in a substantial bandwidth improvement of up to 1000%, relative to a standard 50 Ω termination. An inherent limitation of large area photodiodes, associated with internal resistive elements, was identified and ameliorated, through the design of negative resistance circuits. Altogether, this research resulted in a set of design methods and practical circuits, which will hopefully contribute to wider adoption of VLC systems and may be applied in areas beyond VLC

Design and Implementation of an Integrated Biosensor Platform for Lab-on-a-Chip Diabetic Care Systems

Recent advances in semiconductor processing and microfabrication techniques allow the implementation of complex microstructures in a single platform or lab on chip. These devices require fewer samples, allow lightweight implementation, and offer high sensitivities. However, the use of these microstructures place stringent performance constraints on sensor readout architecture. In glucose sensing for diabetic patients, portable handheld devices are common, and have demonstrated significant performance improvement over the last decade. Fluctuations in glucose levels with patient physiological conditions are highly unpredictable and glucose monitors often require complex control algorithms along with dynamic physiological data. Recent research has focused on long term implantation of the sensor system. Glucose sensors combined with sensor readout, insulin bolus control algorithm, and insulin infusion devices can function as an artificial pancreas. However, challenges remain in integrated glucose sensing which include degradation of electrode sensitivity at the microscale, integration of the electrodes with low power low noise readout electronics, and correlation of fluctuations in glucose levels with other physiological data. This work develops 1) a low power and compact glucose monitoring system and 2) a low power single chip solution for real time physiological feedback in an artificial pancreas system. First, glucose sensor sensitivity and robustness is improved using robust vertically aligned carbon nanofiber (VACNF) microelectrodes. Electrode architectures have been optimized, modeled and verified with physiologically relevant glucose levels. Second, novel potentiostat topologies based on a difference-differential common gate input pair transimpedance amplifier and low-power voltage controlled oscillators have been proposed, mathematically modeled and implemented in a 0.18μm [micrometer] complementary metal oxide semiconductor (CMOS) process. Potentiostat circuits are widely used as the readout electronics in enzymatic electrochemical sensors. The integrated potentiostat with VACNF microelectrodes achieves competitive performance at low power and requires reduced chip space. Third, a low power instrumentation solution consisting of a programmable charge amplifier, an analog feature extractor and a control algorithm has been proposed and implemented to enable continuous physiological data extraction of bowel sounds using a single chip. Abdominal sounds can aid correlation of meal events to glucose levels. The developed integrated sensing systems represent a significant advancement in artificial pancreas systems

Parametric analog signal amplification applied to nanoscale cmos wireless digital transceivers

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer Engineering by the Universidade Nova de Lisboa,Faculdade de Ciências e TecnologiaSignal amplification is required in almost every analog electronic system. However noise is also present, thus imposing limits to the overall circuit performance, e.g., on the sensitivity of the radio transceiver. This drawback has triggered a major research on the field, which has been producing several solutions to achieve amplification with minimum added noise. During the Fifties, an interesting out of mainstream path was followed which was based on variable reactance instead of resistance based amplifiers. The principle of these parametric circuits permits to achieve low noise amplifiers since the controlled variations of pure reactance elements is intrinsically noiseless. The amplification is based on a mixing effect which enables energy transfer from an AC pump source to other related signal frequencies. While the first implementations of these type of amplifiers were already available at that time, the discrete-time version only became visible more recently. This discrete-time version is a promising technique since it is well adapted to the mainstream nanoscale CMOS technology. The technique itself is based on the principle of changing the surface potential of the MOS device while maintaining the transistor gate in a floating state. In order words, the voltage amplification is achieved by changing the capacitance value while maintaining the total charge unchanged during an amplification phase. Since a parametric amplifier is not intrinsically dependent on the transconductance of the MOS transistor, it does not directly suffer from the intrinsic transconductance MOS gain issues verified in nanoscale MOS technologies. As a consequence, open-loop and opamp free structures can further emerge with this additional contribution. This thesis is dedicated to the analysis of parametric amplification with special emphasis on the MOS discrete-time implementation. The use of the latter is supported on the presentation of several circuits where the MOS Parametric Amplifier cell is well suited: small gain amplifier, comparator, discrete-time mixer and filter, and ADC. Relatively to the latter, a high speed time-interleaved pipeline ADC prototype is implemented in a,standard 130 nm CMOS digital technology from United Microelectronics Corporation (UMC). The ADC is fully based on parametric MOS amplification which means that one could achieve a compact and MOS-only implementation. Furthermore, any high speed opamp has not been used in the signal path, being all the amplification steps implemented with open-loop parametric MOS amplifiers. To the author’s knowledge, this is first reported pipeline ADC that extensively used the parametric amplification concept.Fundação para a Ciência e Tecnologia through the projects SPEED, LEADER and IMPAC