High Efficiency Cross-Coupled Charge Pump Circuit with Four-Clock Signals

© Allerton Press, Inc. 2018A fully integrated cross-coupled charge pump circuit for boosting dc-to-dc converter applications with four-clock signals has been proposed. With the new clock scheme, this charge pump eliminates all of the reversion power loss and reduces the ripple voltage. In addition, the largest voltage differences between the terminals of all transistors do not exceed the power supply voltage for solving the gate-oxide overstress problem in the conventional charge pump circuits and enhancing the reliability. This proposed charge pump circuit does not require any extra level shifter; therefore, the power efficiency is increased. The proposed charge pump circuit has been simulated using Spectre in the TSMC 0.18 μm CMOS process. The simulation results show that the maximum voltage conversion efficiency of the new 3-stage cross-coupled circuit with an input voltage of 1.5Vis 99.8%. According to the comparison results of the conventional pump and the enhanced charge pump proposed, the output ripple voltage has been significantly reduced.Peer reviewe

Large second harmonic generation enhancement in SiN waveguides by all-optically induced quasi phase matching

Integrated waveguides exhibiting efficient second-order nonlinearities are crucial to obtain compact and low power optical signal processing devices. Silicon nitride (SiN) has shown second harmonic generation (SHG) capabilities in resonant structures and single-pass devices leveraging intermodal phase matching, which is defined by waveguide design. Lithium niobate allows compensating for the phase mismatch using periodically poled waveguides, however the latter are not reconfigurable and remain difficult to integrate with SiN or silicon (Si) circuits. Here we show the all-optical enhancement of SHG in SiN waveguides by more than 30 dB. We demonstrate that a Watt-level laser causes a periodic modification of the waveguide second-order susceptibility. The resulting second order nonlinear grating has a periodicity allowing for quasi phase matching (QPM) between the pump and SH mode. Moreover, changing the pump wavelength or polarization updates the period, relaxing phase matching constraints imposed by the waveguide geometry. We show that the grating is long term inscribed in the waveguides, and we estimate a second order nonlinearity of the order of 0.3 pm/V, while a maximum conversion efficiency (CE) of 1.8x10-6 W-1 cm-2 is reached

High-efficiency high voltage hybrid charge pump design with an improved chip area

A hybrid charge pump was developed in a 0.13- $\mu \text{m}$ Bipolar-CMOS-DMOS (BCD) process which utilised high drain-source voltage MOS devices and low-voltage integrated metal-insulator-metal (MIM) capacitors. The design consisted of a zero-reversion loss cross-coupled stage and a new self-biased serial-parallel charge pump design. The latter has been shown to have an area reduction of 60% in comparison to a Schottky diode-based Dickson charge pump operating at the same frequency. Post-layout simulations were carried out which demonstrated a peak efficiency of 38% at the output voltage of 18.5 V; the maximum specified output voltage of 27 V was also achieved. A standalone serial-parallel charge pump was shown to have a better transient response and a flatter efficiency curve; these are preferable for time-sensitive applications with a requirement of a broader range of output currents. These findings have significant implications for reducing the total area of implantable high-voltage devices without sacrificing charge pump efficiency or maximum output voltage

An Offset Cancelation Technique for Latch Type Sense Amplifiers

An offset compensation technique for a latch type sense amplifier is proposed in this paper. The proposed scheme is based on the recalibration of the charging/discharging current of the critical nodes which are affected by the device mismatches. The circuit has been designed in a 65 nm CMOS technology with 1.2 V core transistors. The auto-calibration procedure is fully digital. Simulation results are given verifying the operation for sampling a 5 Gb/s signal dissipating only 360 uW