Rapid mapping of digital integrated circuit logic gates via multi-spectral backside imaging

Modern semiconductor integrated circuits are increasingly fabricated at untrusted third party foundries. There now exist myriad security threats of malicious tampering at the hardware level and hence a clear and pressing need for new tools that enable rapid, robust and low-cost validation of circuit layouts. Optical backside imaging offers an attractive platform, but its limited resolution and throughput cannot cope with the nanoscale sizes of modern circuitry and the need to image over a large area. We propose and demonstrate a multi-spectral imaging approach to overcome these obstacles by identifying key circuit elements on the basis of their spectral response. This obviates the need to directly image the nanoscale components that define them, thereby relaxing resolution and spatial sampling requirements by 1 and 2 - 4 orders of magnitude respectively. Our results directly address critical security needs in the integrated circuit supply chain and highlight the potential of spectroscopic techniques to address fundamental resolution obstacles caused by the need to image ever shrinking feature sizes in semiconductor integrated circuits

Modified Level Restorers Using Current Sink and Current Source Inverter Structures for BBL-PT Full Adder

Full adder is an essential component for the design and development of all types of processors like digital signal processors (DSP), microprocessors etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is a significant goal. In this paper, we proposed two modified level restorers using current sink and current source inverter structures for branch-based logic and pass-transistor (BBL-PT) full adder [1]. In BBL-PT full adder, there lies a drawback i.e. voltage step existence that could be eliminated in the proposed logics by using the current sink inverter and current source inverter structures. The proposed full adders are compared with the two standard and well-known logic styles, i.e. conventional static CMOS logic and Complementary Pass transistor Logic (CPL), demonstrated the good delay performance. The implementation of 8-bit ripple carry adder based on proposed full adders are finally demonstrated. The CPL 8-bit RCA and as well as the proposed ones is having better delay performance than the static CMOS and BBL-PT 8-bit RCA. The performance of the proposed BBL-PT cell with current sink & current source inverter structures are examined using PSPICE and the model parameters of a 0.13 µm CMOS process

Advancing Hardware Security Using Polymorphic and Stochastic Spin-Hall Effect Devices

Protecting intellectual property (IP) in electronic circuits has become a serious challenge in recent years. Logic locking/encryption and layout camouflaging are two prominent techniques for IP protection. Most existing approaches, however, particularly those focused on CMOS integration, incur excessive design overheads resulting from their need for additional circuit structures or device-level modifications. This work leverages the innate polymorphism of an emerging spin-based device, called the giant spin-Hall effect (GSHE) switch, to simultaneously enable locking and camouflaging within a single instance. Using the GSHE switch, we propose a powerful primitive that enables cloaking all the 16 Boolean functions possible for two inputs. We conduct a comprehensive study using state-of-the-art Boolean satisfiability (SAT) attacks to demonstrate the superior resilience of the proposed primitive in comparison to several others in the literature. While we tailor the primitive for deterministic computation, it can readily support stochastic computation; we argue that stochastic behavior can break most, if not all, existing SAT attacks. Finally, we discuss the resilience of the primitive against various side-channel attacks as well as invasive monitoring at runtime, which are arguably even more concerning threats than SAT attacks.Comment: Published in Proc. Design, Automation and Test in Europe (DATE) 201

DESIGN AND PERFORMANCE ANALYSIS OF FULL ADDER USING 6-T XOR–XNOR CELL

In this paper, the design and simulation of a high-speed, low power 6-T XOR-XNOR circuit is carried out. Also, the design and simulation of 1-bit hybrid full adder (consisting of 16 transistors) using XOR-XNOR circuit, sum, and carry, is performed to improve the area and speed performance. Its performance is being compared with full adder designs with 20 and 18 transistors, respectively. The performance of the proposed circuits is measured by simulating them in Microwind tool using 180 and 90nm CMOS technology. The performance of the proposed circuit is measured in terms of power, delay, and PDP (Power Delay Product)