1,286 research outputs found
Systematic Comparison of HF CMOS Transconductors
Transconductors are commonly used as active elements in high-frequency (HF) filters, amplifiers, mixers, and oscillators. This paper reviews transconductor design by focusing on the V-I kernel that determines the key transconductor properties. Based on bandwidth considerations, simple V-I kernels with few or no internal nodes are preferred. In a systematic way, virtually all simple kernels published in literature are generated. This is done in two steps: 1) basic 3-terminal transconductors are covered and 2) then five different techniques to combine two of them in a composite V-I kernel. In order to compare transconductors in a fair way, a normalized signal-to-noise ratio (NSNR) is defined. The basic V-I kernels and the five classes of composite V-I kernels are then compared, leading to insight in the key mechanisms that affect NSNR. Symbolic equations are derived to estimate NSNR, while simulations with more advanced MOSFET models verify the results. The results show a strong tradeoff between NSNR and transconductance tuning range. Resistively generated MOSFETs render the best NSNR results and are robust for future technology developments
FGMOS Based Voltage-Controlled Grounded Resistor
This paper proposes a new floating gate MOSFET (FGMOS) based voltage-controlled grounded resistor. In the proposed circuit FGMOS operating in the ohmic region is linearized by another conventional MOSFET operating in the saturation region. The major advantages of FGMOS based voltage-controlled grounded resistor (FGVCGR) are simplicity, low total harmonic distortion (THD), and low power consumption. A simple application of this FGVCGR as a tunable high-pass filter is also suggested. The proposed circuits operate at the supply voltages of +/-0.75 V. The circuits are designed and simulated using SPICE in 0.25-µm CMOS technology. The simulation results of FGVCGR demonstrate a THD of 0.28% for the input signal 0.32 Vpp at 45 kHz, and a maximum power consumption of 254 µW
Power and area efficient MOSFET-C filter for very low frequency applications
New circuit design techniques for implementing very high-valued resistors are presented, significantly improving power and area efficiency of analog front-end signal processing in ultra-low power biomedical systems. Ranging in value from few hundreds of \hbox{M}\Upomega to few hundreds of \hbox{G}\Upomega , the proposed floating resistors occupy a very small area, and produce accurately tunable characteristics. Using this approach, a low-pass MOSFET-C filter with tunable cutoff frequency (f C =20Hz-184kHz) has been implemented in a conventional 0.18ÎĽm CMOS technology. Occupying 0.045mm2/pole, the power consumption of this filter is 540 pW/Hz/pole with a measured IMFDR of 70 d
ULTRA LOW POWER FSK RECEIVER AND RF ENERGY HARVESTER
This thesis focuses on low power receiver design and energy harvesting techniques as methods for intelligently managing energy usage and energy sources. The goal is to build an inexhaustibly powered communication system that can be widely applied, such as through wireless sensor networks (WSNs). Low power circuit design and smart power management are techniques that are often used to extend the lifetime of such mobile devices. Both methods are utilized here to optimize power usage and sources.
RF energy is a promising ambient energy source that is widely available in urban areas and which we investigate in detail. A harvester circuit is modeled and analyzed in detail at low power input. Based on the circuit analysis, a design procedure is given for a narrowband energy harvester. The antenna and harvester co-design methodology improves RF to DC energy conversion efficiency. The strategy of co-design of the antenna and the harvester creates opportunities to optimize the system power conversion efficiency. Previous surveys have found that ambient RF energy is spread broadly over the frequency domain; however, here it is demonstrated that it is theoretically impossible to harvest RF energy over a wide frequency band if the ambient RF energy source(s) are weak, owing to the voltage requirements. It is found that most of the ambient RF energy lies in a series of narrow bands.
Two different versions of harvesters have been designed, fabricated, and tested. The simulated and measured results demonstrate a dual-band energy harvester that obtains over 9% efficiency for two different bands (900MHz and 1800MHz) at an input power as low as -19dBm. The DC output voltage of this harvester is over 1V, which can be used to recharge the battery to form an inexhaustibly powered communication system.
A new phase locked loop based receiver architecture is developed to avoid the significant conversion losses associated with OOK architectures. This also helps to minimize power consumption. A new low power mixer circuit has also been designed, and a detailed analysis is provided. Based on the mixer, a low power phase locked loop (PLL) based receiver has been designed, fabricated and measured.
A power management circuit and a low power transceiver system have also been co-designed to provide a system on chip solution. The low power voltage regulator is designed to handle a variety of battery voltage, environmental temperature, and load conditions. The whole system can work with a battery and an application specific integrated circuit (ASIC) as a sensor node of a WSN network
Monitor-Based In-Field Wearout Mitigation for CMOS RF Integrated Circuits
abstract: Performance failure due to aging is an increasing concern for RF circuits. While most aging studies are focused on the concept of mean-time-to-failure, for analog circuits, aging results in continuous degradation in performance before it causes catastrophic failures. In this regard, the lifetime of RF/analog circuits, which is defined as the point where at least one specification fails, is not just determined by aging at the device level, but also by the slack in the specifications, process variations, and the stress conditions on the devices. In this dissertation, firstly, a methodology for analyzing the performance degradation of RF circuits caused by aging mechanisms in MOSFET devices at design-time (pre-silicon) is presented. An algorithm to determine reliability hotspots in the circuit is proposed and design-time optimization methods to enhance the lifetime by making the most likely to fail circuit components more reliable is performed. RF circuits are used as test cases to demonstrate that the lifetime can be enhanced using the proposed design-time technique with low area and no performance impact. Secondly, in-field monitoring and recovering technique for the performance of aged RF circuits is discussed. The proposed in-field technique is based on two phases: During the design time, degradation profiles of the aged circuit are obtained through simulations. From these profiles, hotspot identification of aged RF circuits are conducted and the circuit variable that is easy to measure but highly correlated to the performance of the primary circuit is determined for a monitoring purpose. After deployment, an on-chip DC monitor is periodically activated and its results are used to monitor, and if necessary, recover the circuit performances degraded by aging mechanisms. It is also necessary to co-design the monitoring and recovery mechanism along with the primary circuit for minimal performance impact. A low noise amplifier (LNA) and LC-tank oscillators are fabricated for case studies to demonstrate that the lifetime can be enhanced using the proposed monitoring and recovery techniques in the field. Experimental results with fabricated LNA/oscillator chips show the performance degradation from the accelerated stress conditions and this loss can be recovered by the proposed mitigation scheme.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201
Design of an ultra-low-power integrated amplifier for cardiac signal implantable sensors
Al giorno d'oggi, il monitoraggio della salute è un'area di ricerca cruciale, data la crescente necessità di rilevare i parametri vitali per ottenere diagnosi accurate in tempi brevi, raccogliere continuamente informazioni sullo stato di salute dei pazienti e intervenire rapidamente in circostanze critiche. Questa tesi si colloca nell'ambito della registrazione di segnali ECG, essendo di estrema importanza per la diagnosi delle malattie cardiovascolari. I dispositivi impiantabili sono spesso utilizzati per questo scopo, in quanto consentono misurazioni poco invasive, ottenendo così segnali affidabili con una migliore reiezione di interferenze e artefatti. Viene presentato un amplificatore a bassissima potenza per sensori impiantabili. Il sistema nel suo complesso ha una batteria di capacità limitata, il che rende il consumo di potenza un aspetto fondamentale nelle scelte di progettazione. Inoltre, i segnali ECG hanno un'ampiezza limitata e sono spesso affetti da ampi offset in DC, evidenziando così la necessità di progettare amplificatori accoppiati in AC, che introducano livelli di rumore minimi. Questa topologia circuitale impiega amplificatori operazionali di transconduttanza (OTA) realizzati con inverter di tipo stacked, che sommano ciascuna transconduttanza, utilizzando la stessa corrente, implementando quindi la tecnica del riutilizzo di corrente, al fine di migliorare l'efficienza di rumore e di potenza, fornendo al contempo un elevato guadagno. Il progetto è stato implementato in un processo CMOS a 130 nm.
Si presenta quindi un amplificatore operazionale di transconduttanza basato su inverter di tipo stacked, pensato per processare segnali ECG. Esso presenta un guadagno di modo differenziale pari a 23.9 dB in banda, una larghezza di banda di 10.5 kHz, un rapporto di reiezione di modo comune CMRR di 59 dB, un rapporto di reiezione della tensione di alimentazione PSRR di 62 dB e rumore termico pari a 116 nV/Hz.Nowadays, health monitoring is a crucial area of research, given the increasing need to detect vital parameters in order to obtain accurate diagnoses in a short time, continuously collect informations about the health status of patients, and quickly intervene in critical circumstances. This thesis focuses on electrocardiogram (ECG) signals recording, being of the utmost importance for the diagnosis of cardiovascular diseases. Implantable devices are often used for this purpose, because they allow unobtrusive measurements, resulting in reliable signals with better rejection of interferences and artifacts. An ultra-low power amplifier intended for implantable sensors is presented. The overall system has a limited battery capacity, thus making power consumption a key aspect when it comes to design choices. Furthermore, ECG signals have a limited amplitude and are often affected by large DC offsets, thus emphasizing the need to design ac-coupled amplifiers that introduce minimal noise levels. This circuit topology employs stacked inverter-based operational transconductance amplifiers (OTAs), that add up each transconductance, but using the same current, thereby implementing the current-reuse technique, in order to improve noise and power efficiency, while providing high gain. The design was implemented in a 130-nm CMOS process.
A stacked inverter-based operational transconductance amplifier (OTA) designed to process ECG signals is then presented. It achieves a differential mode gain of 23.9 dB in-band, a bandwidth of 10.5 kHZ, a common-mode rejection ratio CMRR of 59 dB, a power supply rejection ratio PSRR of 62 dB and thermal noise of 116 nV/Hz
High Frequency, High Linearity and Low Noise Digital to Time Converter for Phase Adjustment
Nowadays, fast communication systems have become vital for our lifestyle. As a result, the digital
PLL fulfils a very important role as frequency synthesizer, demodulator or distributor of clock signals
in microprocessors and similar digital circuits. Thus, the correction of the signal using a phase adjust-
ment is essential for the good operation of the PLL.
In this work, it is proposed a variable slope digital to time converter (DTC), as a programmable
delay line, used for the correction of the phase of a digital PLL. The work is focused on the study of the
performance of the circuit, through the evaluation of fundamental parameters such as RMS jitter, line-
arity, resolution and delay range.
Accordingly, it is employed a 4-bit topology using 130 nm MOSFET technology. The in-
tended DTC takes advantage of CMOS inverters, due to their simplicity and low noise, and capacitors,
for the programmable delay RC network. The DTC functioning is based on the activation of switching
transistors to trigger the programmable capacitors, through a code to define the number of capacitors
that introduce delay. The circuit is complemented with a simple CMOS inverter as a comparator that
triggers when the threshold voltage is attained and an output buffer employed to correct the slopes of
the signal.
The proposed DTC proposed is a single-ended architecture that achieves 52.50 fs RMS jitter, and
the resulting DNL and INL are equivalent to 0.1124 LSB and 0.09773 LSB, respectively. The 4-bit de-
lay line has a resolution of 15.2 ps, an area of 0.018 mm2 and a power consumption of 62.8 ÎĽW from
a 1.2 V low dropout regulator (LDO).Atualmente, os sistemas de comunicação rápida tornaram-se vitais para o nosso estilo de vida.
Como resultado, a PLL digital apresenta um papel importante em funções como sintetizador de frequên-
cia, demodulador ou distribuidor de sinais de relĂłgio de microprocessadores ou circuitos digitais seme-
lhantes. Assim, a correção do sinal utilizando um ajuste de fase é essencial para o bom funcionamento
da PLL.
Neste trabalho, é proposto um conversor digital para tempo de inclinação de curva variável, como
uma linha de atraso programável, utilizada para corrigir a fase de uma PLL digital.
Este trabalho é focado no estudo da performance do dispositivo, através da avaliação de parâme-
tros fundamentais como RMS jitter, linearidade, resolução e range de atraso.
Desta forma, a topologia implementada utiliza 4 bits e tecnologia MOSFET 130 . O
conversor digital para tempo Ă© criado utilizando inversores CMOS, que tĂŞm as vantagens de apresentar
simplicidade e baixo ruĂdo, e condensadores, utilizados para programar a rede de atraso de RC. Este
funciona com base na ativação de transĂstores, empregues como interruptores para acionar os conden-
sadores programáveis, através de um código que define o número de condensadores ligados que intro-
duzem atraso. O circuito Ă© complementado com um inversor CMOS como comparador que Ă© acionado
quando a voltagem de threshold Ă© atingida e um buffer de saĂda implementado para corrigir a inclinação
das curvas.
O respetivo conversor apresenta uma arquitetura com uma Ăşnica saĂda que Ă© capaz de atingir
52.50 fs RMS jitter, e possuĂ DNL e INL equivalente a 0.1124 LSB e 0.09773 LSB, respetivamente. A
linha de atraso de 4 bits tem uma resolução de 15.2 ps, uma área de 0.018 mm2 e um consumo de
potĂŞncia de 62.8 ÎĽW vindo de um regulador de baixa queda de tensĂŁo de 1.2 V
The design of active resistors and transductors in a CMOS technology
Merged with duplicate record 10026.1/2618 on 07.20.2017 by CS (TIS)This thesis surveys linearisation techniques for implementing monolithic MOS
active resistors and transconductors, and investigates the design of linear tunable
resistors and transconductors. Improving linearity and tunability in the presence
of non-ideal factors such as bulk modulation, mobility-degradation effects and mismatch
of transistors is a principal objective. A family of new non-saturation-mode
resistors and two novel saturation-mode transconductors are developed. Where
possible, approximate analytical expressions are derived to explain the principles
of operation. Performance comparisons of the new structures are made with other
well-known circuits and their relative advantages and disadvantages evaluated.
Experimental and simulation results are presented which validate the proposed
linearisation techniques. It is shown that the proposed family of resistors offers
improved linearity whilst the transconductors combine extended tunability with
low distortion. Continuous-time filter examples are given to demonstrate the
potential of these circuits for application in analogue signal-processing tasks.GEC Plessey Semiconductors, Plymout
Low temperature sensitivity CMOS transconductor based on GZTC MOSFET condition
Complementary Metal Oxide Semiconductor (CMOS) Transconductors, or Gm cells, are key building blocks to implement a large variety of analog circuits such as adjustable filters, multipliers, controlled oscillators and amplifiers. Usually temperature stability is a must in such applications, and herein we define all required conditions to design low thermal sensitivity Gm cells by biasing MOSFETs at Transconductance Zero Temperature Condition (GZTC). This special bias condition is analyzed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are designed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits have been simulated in a 130 nm CMOS commercial process, resulting in improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/ÂşC
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