DESIGN OF NEW HIGH SPEED MULTI OUTPUT CARRY LOOK-AHEAD ADDERS

The carry look-ahead adders are designed till now by using standard 4 bit Manchester carry chain. Due to its limited carry chain length, the carries of the adders are computed using 4 bit carry chain. This leads to slow down the operation. A high speed 8 bit (MCC) adder in multi output domino CMOS logic is designed in this thesis. Due to its limited carry chain length this high speed MCC uses 2 separate 4-bit MCC. The 2 MCC namely odd carry chain and even carry chain are computed in parallel to increase the speed of the operation. This technique has been applied for the design of 8 bit adders in multi output domino logic and the simulation results are verified. Results prove that 8 bit MCC produces less delay compared to conventional 4 bit delay. The reduced delay realizes better speed compared to the conventional designs. The existing design and the previous designs are designed and simulated using Mentor Graphics. The delay of these designs is compared with 8 bit input and with 50 nm technology file. Implementation results reveal that the high speed comparator has delay of 37.47% less compared to the conventional designs used for comparison when operated at 50 MHz

FPGA adders: performance evaluation and optimal design

Delay models and cost analyses developed for ASIC technology are not useful in designing and implementing FPGA devices. The authors discuss costs and operational delays of fixed-point adders on Xilinx 4000 series devices and propose timing models and optimization schemes for carry-skip and carry-select adders.published_or_final_versio

Arithmetic logic UNIT (ALU) design using reconfigurable CMOS logic

Using the reconfigurable logic of multi-input floating gate MOSFETs, a 4-bit ALU has been designed for 3V operation. The ALU can perform four arithmetic and four logical operations. Multi- input floating gate (MIFG) transistors have been promising in realizing increased functionality on a chip. A multi- input floating gate MOS transistor accepts multiple inputs signals, calculates the weighted sum of all input signals and then controls the ON and OFF states of the transistor. This enhances the transistor function to more than just switching. This changes the way a logic function can be realized. Implementing a design using multi-input floating gate MOSFETs brings about reduction in transis tor count and number of interconnections. The advantage of bringing down the number of devices is that a design becomes area efficient and power consumption reduces. There are several applications that stress on smaller chip area and reduced power. Multi- input floating gate devices have their use in memories, analog and digital circuits. In the present work we have shown successful implementation of multi- input floating gate MOSFETs in ALU design. A comparison has been made between adders using different design methods w.r.t transistor count. It is seen that our design, implemented using multi-input floating gate MOSFETs, uses the least number of transistors when compared to other designs. The design was fabricated using double polysilicon standard CMOS process by MOSIS in 1.5mm technology. The experimental waveforms and delay measurements have also been presented

A Low-Area, Energy-Efficient 64-Bit Reconfigurable Carry Select Modified Tree-Based Adder for Media Signal Processing

Multimedia systems play an essential part in our daily lives and have drastically improved the quality of life over time. Multimedia devices like cellphones, radios, televisions, and computers require low-area and low-power reconfigurable adders to process greedy computation algorithms for the real-time audio/video signal and image processing such as discrete cosine transform, inverse discrete cosine transform, and fast Fourier transform, etc. In this thesis, a novel 64-bit reconfigurable adder is proposed and implemented to reduce the area and power consumption. This adder can be run-time reconfigured to different reconfigurable word lengths, i.e., one 64- bit, two 32-bits, four 16-bits or eight 8-bits addition, depending on the partition signal command. A Carry Select Modified Tree (CSMT) based adder is used in the reconfigurable adder to reduce the area by 22 % and the power consumption by 47 % when compared to the conventional design. The proposed adder, implemented in 180 nm CMOS technology at 1.8-volt supply, has a worst-case Delay of 20.67 nanoseconds with an overall area of 36,417 μm² and power consumption of 447.93 μW

Performance evaluation of FPGA implementations of high-speed addition algorithms

Driven by the excellent properties of FPGAs and the need for high-performance and flexible computing machines, interest in FPGA-based computing machines has increased dramatically. Fixed-point adders are essential building blocks of any computing systems. In this work, various high-speed addition algorithms are implemented in FPGAs devices, and their performance is evaluated with the objective of finding and developing the most appropriate addition algorithms for implementing in FPGAs, and laying the ground-work for evaluating and constructing FPGA-based computing machines. The results demonstrate that the performance of adders built with the FPGAs dedicated carry logic combined with some other addition algorithms will be greatly improved, especially for larger adders.published_or_final_versio

A comparative analysis of parallel prefix adders in 32nm and 45nm static CMOS technology

textBinary adders form a major part in various arithmetic logical operation units including multipliers, dividers and digital signal processors. Parallel prefix adders represent a set of efficient structures for binary addition, greatly suited for VLSI implementation due to their regularity and speed. This report is focused on the comparative analysis of 5 major types of parallel prefix adder frameworks namely Kooge-Stone, Knowles adders, Brent-Kung, Han-Carlson and Ladner-Fischer adders implemented in Synopsys's SAED 32nm static CMOS technology operating at 1.05V for 8-bit, 16-bit and 32-bit input vectors based on power, performance and area (PPA) metrics. The process technology is modeled with 9 metal tracks. Power, performance and area metrics based on circuit simulations are used for comparison. The metrics are compared across SAED 32nm and FreePDK 45nm technology to quantify the impact of technology on architecture.Electrical and Computer Engineerin

HIGH-SPEED MULTIOUTPUT CLA-ADDERS USING 8-BIT MCC ADDER IN DOMINO LOGIC

Adders are the critical parts of processor circuits. The performance of processors increases by improving the performance and functionality of adders. Carry look-ahead (CLA) adder’s principle remains dominant in High-speed adder architectures, so the carry delay can be improved by calculating each stage in parallel. In this project by using an 8-bit Manchester carry chain (MCC) adder block in multi output domino CMOS logic. The even and odd carries of this adder are computed in parallel by two independent 4-bit carry chains. Implementation of wider adders based on the use of 8-bit adder module improves the operating speed compared to adders based on the standard 4-bit MCC adder module. Proposed design technique can be used for the implementation of 8, 16, 32 and 64 bit adders in multi output domino logic by using mentor graphics

THE METHODS OF IMPROVING THE SPEED OF CLA ADDERS IN DOMINO LOGIC

Adders are the critical parts of processor circuits. The performance of processors increases by improving the performance and functionality of adders. Carry look-ahead (CLA) adder’s principle remains dominant in High-speed adder architectures, so the carry delay can be improved by calculating each stage in parallel. In this paper by using an 4-bit Manchester carry chain (MCC) adder block in multi output domino CMOS logic. The even and odd carries of this adder are computed in parallel by two independent 2-bit carry chains. Implementation of wider adders based on the use of 4-bit adder module improves the operating speed compared to adders based on the standard 4-bit MCC adder module. Proposed design technique can be used for the implementation of 4, 8, 16 and 32 bit adders in multi output domino logic by using mentor graphics

Siwa: A custom RISC-V based system on chip (SOC) for low power medical applications

This work introduces the development of Siwa, a RISC-V RV32I 32-bit based core, intended as a flexible control platform for highly integrated implantable biomedical applications, and implemented on a commercial 0.18 m high voltage (HV) CMOS technology. Simulations show that Siwa can outperform commercial micro-controllers commonly used in the medical industry as control units for implantable devices, with energy requirements below the 50 pJ per clock cycle.Agencia Nacional de Investigación e Innovació