Millimeter-Wave Super-Regenerative Receivers for Wireless Communication and Radar

Today’s world is becoming increasingly automated and interconnected with billions of smart devices coming online, leading to a steep rise in energy consumption from small microelectronics. This coincides with an urgent push to transform global energy production to green energies, causing disruptions and energy shortages, and making the case for efficient energy use ever more pressing. Two major areas where high growth is expected are the fields of wireless communication and radar sensors. Millimeter-wave frequency bands are planned for fifth-generation (5G) and sixth-generation (6G) cellular communication standards, as well as automotive frequency-modulated continuous wave (FMCW) radar systems for driving assistance and automation. Fast silicon-based technologies enable these advances by operating at high maximum frequencies, such as the silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technologies. However, even the fastest transistors suffer from low and energy expensive gains at millimeter-wave frequencies. Rather than incremental improvements in circuit efficiency using conventional approaches, a disruptive revolution for green microelectronics could be enabled by exploring the low-power benefits of the super-regenerative receiver for some applications. The super-regenerative receiver uses a regenerative oscillator circuit to increase the gain by positive feedback, through coupling energy from the output back into the input. Careful bias and control of the circuit enables a very large gain from a small number of transistors and a very low energy dissipation. Thus, the super-regenerative oscillator could be used to replace amplifier circuits in high data rate wireless communication systems, or as active reflectors to increase the range of FMCW radar systems, greatly reducing the power consumption. The work in this thesis presents fundamental scientific research into the topic of energy-efficient millimeter-wave super-regenerative receivers for use in civilian wireless communication and radar applications. This research work covers the theory, analysis, and simulations, all the way up to the proof of concept, hardware realization, and experimental characterization. Analysis and modeling of regenerative oscillator circuits is presented and used to improve the understanding of the circuit operation, as well as design goals according to the specific application needs. Integrated circuits are investigated and characterized as a proof of concept for a high data rate wireless communication system operating between 140–220 GHz, and an automotive radar system operating at 60 GHz. Amplitude and phase regeneration capabilities for complex modulation are investigated, and principles for spectrum characterization are derived. The circuits are designed and fabricated in a 130 nm SiGe HBT technology, combining bipolar and complementary metal-oxide semiconductor (BiCMOS) transistors. To prove the feasibility of the research concepts, the work achieves a wireless communication link at 16 Gbit/s over 20 cm distance with quadrature amplitude modulation (QAM), which is a world record for the highest data rate ever reported in super-regenerative circuits. This was powered by a super-regenerative oscillator circuit operating at 180 GHz and providing 58 dB of gain. Energy efficiency is also considerably high, drawing 8.8 mW of dc power consumption, which corresponds to a highly efficient 0.6 pJ/bit. Packaging and module integration innovations were implemented for the system experiments, and additional broadband circuits were investigated to generate custom quench waveforms to further enhance the data rate. For radar active reflectors, a regenerative gain of 80 dB is achieved at 60 GHz from a single circuit, which is the best in its frequency range, despite a low dc power consumption of 25 mW

Analysis and simulation methods for free-running, injection-locked and super-regenerative oscillators

RESUMEN: En los últimos años, muchos esfuerzos han sido dedicados al desarrollo de técnicas complementarias para el análisis de circuitos autónomos de microondas. Estas técnicas están pensadas para su uso en combinación con balance armónico, ampliamente usado para el análisis a frecuencias de microondas. De hecho, balance armónico sufre de restricciones cuando se utiliza para el análisis de circuitos autónomos, en su mayoría debidos a su falta de sensibilidad a las propiedades de estabilidad de la solución que se genera o se extingue mediante bifurcaciones. En esta tesis doctoral se presentan nuevos métodos de simulación y análisis para la caracterización y modelado de osciladores libres, sincronizados y superregenerativos. Todos los resultados obtenidos mediante los nuevos métodos de simulación y análisis han sido comparados satisfactoriamente con otras técnicas de simulación y con medidas.ABSTRACT: In the last years, numerous efforts have been devoted to the development of complementary analysis tools for autonomous microwave circuits. They are intended to be applied in combination with the harmonic-balance (HB) method, widely used at microwave frequencies. In fact, HB suffers from a number of shortcomings when dealing with autonomous circuits, mostly due the fact that it is insensitive to the stability properties of the solution, generated and extinguished through bifurcation phenomena. Here, new simulation and analysis methodologies for the characterization and modeling of free-running, injection-locked and super-regenerative oscillators have been proposed to overcome these problems when using commercial software. Results from the different new analysis methodologies have been successfully compared with independent simulations and with measurements

An Optical Grooming Switch for High-Speed Traffic Aggregation in Time, Space and Wavelength

In this book a novel optical switch is designed, developed, and tested. The switch integrates optical switching, transparent traffic aggregation/grooming, and optical regener-ation. Innovative switch subsystems are developed that enable these functionalities, including all-optical OTDM-to-WDM converters. High capacity ring interconnection between metro-core rings, carrying 130 Gbit/s OTDM traffic, and metro-access rings carring 43 Gbit/s WDM traffic is experimentally demonstrated. The developed switch features flexibility in bandwidth provisioning, scalability to higher traffic volumes, and backward compatibility with existing network implementations in a future-proof way

Wireless wire - ultra-low-power and high-data-rate wireless communication systems

With the rapid development of communication technologies, wireless personal-area communication systems gain momentum and become increasingly important. When the market gets gradually saturated and the technology becomes much more mature, new demands on higher throughput push the wireless communication further into the high-frequency and high-data-rate direction. For example, in the IEEE 802.15.3c standard, a 60-GHz physical layer is specified, which occupies the unlicensed 57 to 64 GHz band and supports gigabit links for applications such as wireless downloading and data streaming. Along with the progress, however, both wireless protocols and physical systems and devices start to become very complex. Due to the limited cut-off frequency of the technology and high parasitic and noise levels at high frequency bands, the power consumption of these systems, especially of the RF front-ends, increases significantly. The reason behind this is that RF performance does not scale with technology at the same rate as digital baseband circuits. Based on the challenges encountered, the wireless-wire system is proposed for the millimeter wave high-data-rate communication. In this system, beamsteering directional communication front-ends are used, which confine the RF power within a narrow beam and increase the level of the equivalent isotropic radiation power by a factor equal to the number of antenna elements. Since extra gain is obtained from the antenna beamsteering, less front-end gain is required, which will reduce the power consumption accordingly. Besides, the narrow beam also reduces the interference level to other nodes. In order to minimize the system average power consumption, an ultra-low power asynchronous duty-cycled wake-up receiver is added to listen to the channel and control the communication modes. The main receiver is switched on by the wake-up receiver only when the communication is identified while in other cases it will always be in sleep mode with virtually no power consumed. Before transmitting the payload, the event-triggered transmitter will send a wake-up beacon to the wake-up receiver. As long as the wake-up beacon is longer than one cycle of the wake-up receiver, it can be captured and identified. Furthermore, by adopting a frequency-sweeping injection locking oscillator, the wake-up receiver is able to achieve good sensitivity, low latency and wide bandwidth simultaneously. In this way, high-data-rate communication can be achieved with ultra-low average power consumption. System power optimization is achieved by optimizing the antenna number, data rate, modulation scheme, transceiver architecture, and transceiver circuitries with regards to particular application scenarios. Cross-layer power optimization is performed as well. In order to verify the most critical elements of this new approach, a W-band injection-locked oscillator and the wake-up receiver have been designed and implemented in standard TSMC 65-nm CMOS technology. It can be seen from the measurement results that the wake-up receiver is able to achieve about -60 dBm sensitivity, 10 mW peak power consumption and 8.5 µs worst-case latency simultaneously. When applying a duty-cycling scheme, the average power of the wake-up receiver becomes lower than 10 µW if the event frequency is 1000 times/day, which matches battery-based or energy harvesting-based wireless applications. A 4-path phased-array main receiver is simulated working with 1 Gbps data rate and on-off-keying modulation. The average power consumption is 10 µW with 10 Gb communication data per day

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

A Low-Power BFSK/OOK Transmitter for Wireless Sensors

In recent years, significant improvements in semiconductor technology have allowed consistent development of wireless chipsets in terms of functionality and form factor. This has opened up a broad range of applications for implantable wireless sensors and telemetry devices in multiple categories, such as military, industrial, and medical uses. The nature of these applications often requires the wireless sensors to be low-weight and energy-efficient to achieve long battery life. Among the various functions of these sensors, the communication block, used to transmit the gathered data, is typically the most power-hungry block. In typical wireless sensor networks, transmission range is below 10 meters and required radiated power is below 1 milliwatt. In such cases, power consumption of the frequency-synthesis circuits prior to the power amplifier of the transmitter becomes significant. Reducing this power consumption is currently the focus of various research endeavors. A popular method of achieving this goal is using a direct-modulation transmitter where the generated carrier is directly modulated with baseband data using simple modulation schemes. Among the different variations of direct-modulation transmitters, transmitters using unlocked digitally-controlled oscillators and transmitters with injection or resonator-locked oscillators are widely investigated because of their simple structure. These transmitters can achieve low-power and stable operation either with the help of recalibration or by sacrificing tuning capability. In contrast, phase-locked-loop-based (PLL) transmitters are less researched. The PLL uses a feedback loop to lock the carrier to a reference frequency with a programmable ratio and thus achieves good frequency stability and convenient tunability. This work focuses on PLL-based transmitters. The initial goal of this work is to reduce the power consumption of the oscillator and frequency divider, the two most power-consuming blocks in a PLL. Novel topologies for these two blocks are proposed which achieve ultra-low-power operation. Along with measured performance, mathematical analysis to derive rule-of-thumb design approaches are presented. Finally, the full transmitter is implemented using these blocks in a 130 nanometer CMOS process and is successfully tested for low-power operation

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort

Optical sampling and metrology using a soliton-effect compression pulse source

A low jitter optical pulse source for applications including optical sampling and optical metrology was modelled and then experimentally implemented using photonic components. Dispersion and non-linear fibre effects were utilised to compress a periodic optical waveform to generate pulses of the order of 10 picoseconds duration, via soliton-effect compression. Attractive features of this pulse source include electronically tuneable repetition rates greater than 1.5 GHz, ultra-short pulse duration (10-15 ps), and low timing jitter as measured by both harmonic analysis and single-sideband (SSB) phase noise measurements. The experimental implementation of the modelled compression scheme is discussed, including the successful removal of stimulated Brillouin scattering (SBS) through linewidth broadening by injection dithering or phase modulation. Timing jitter analysis identifies many unwanted artefacts generated by the SBS suppression methods, hence an experimental arrangement is devised (and was subsequently patented) which ensures that there are no phase modulation spikes present on the SSB phase noise spectrum over the offset range of interest for optical sampling applications, 10Hz-Nyquist. It is believed that this is the first detailed timing jitter study of a soliton-effect compression scheme. The soliton-effect compression pulses are then used to perform what is believed to be the first demonstration of optical sampling using this type of pulse source. The pulse source was also optimised for use in a novel optical metrology (range finding) system, which is being developed and patented under European Space Agency funding as an enabling technology for formation flying satellite missions. This new approach to optical metrology, known as Scanning Interferometric Pulse Overlap Detection (SIPOD), is based on scanning the optical pulse repetition rate to find the specific frequencies which allow the return pulses from the outlying satellite, i.e. the measurement arm, to overlap exactly with a reference pulse set on the hub satellite. By superimposing a low frequency phase modulation onto the optical pulse train, it is possible to detect the pulse overlap condition using conventional heterodyne detection. By rapidly scanning the pulse repetition rate to find two frequencies which provide the overlapping pulse condition, high precision optical pulses can be used to provide high resolution unambiguous range information, using only relatively simple electronic detection circuitry. SIPOD’s maximum longitudinal range measurement is limited only by the coherence length of the laser, which can be many tens of kilometres. Range measurements have been made to better than 10 microns resolution over extended duration trial periods, at measurement update rates of up to 470 Hz. This system is currently scheduled to fly on ESA’s PROBA-3 mission in 2012 to measure the intersatellite spacing for a two satellite coronagraph instrument. In summary, this thesis is believed to present three novel areas of research: the first detailed jitter characterisation of a soliton-effect compression source, the first optical sampling using such a compression source, and a novel optical metrology range finding system, known as SIPOD, which utilises the tuneable repetition rate and highly stable nature of the compression source pulses

Energy Aware RF Transceiver for Wireless Body Area Networks (WBAN)

Ph.DDOCTOR OF PHILOSOPH

Multi-Loop-Ring-Oscillator Design and Analysis for Sub-Micron CMOS

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort